公开(公告)号：US09240384B2

公开(公告)日：2016-01-19

申请号：US13621804

申请日：2012-09-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Qing Zhang ,  Haijing Cao

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0231 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/11009 ,  H01L2224/11019 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/05552

Abstract: A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

Abstract translation: 半导体器件具有形成在衬底上的第一导电层。 第一绝缘层形成在衬底和第一导电层上。 在第一导电层和第一绝缘层上形成第二导电层。 在第一绝缘层和第二导电层上形成第二绝缘层。 第二绝缘层在第二绝缘材料的表面和第二导电层的表面之间具有侧壁。 在第二绝缘层和第二导电层的表面上形成保护层。 保护层遵循第二绝缘层和第二导电层的表面和侧壁的轮廓。 在第二导电层的表面上形成凸块，并且与第二绝缘层相邻的部分形成保护层。 保护层保护第二绝缘层。

公开(公告)号：US09224693B2

公开(公告)日：2015-12-29

申请号：US14326237

申请日：2014-07-08

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Seung Wook Yoon

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/5384 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/19 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/48247 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die mounted over a carrier. An encapsulant is deposited over the semiconductor die and carrier. An insulating layer is formed over the semiconductor die and encapsulant. A plurality of first vias is formed through the insulating layer and semiconductor die while mounted to the carrier. A plurality of second vias is formed through the insulating layer and encapsulant in the same direction as the first vias while the semiconductor die is mounted to the carrier. An electrically conductive material is deposited in the first vias to form conductive TSV and in the second vias to form conductive TMV. A first interconnect structure is formed over the insulating layer and electrically connected to the TSV and TMV. The carrier is removed. A second interconnect structure is formed over the semiconductor die and encapsulant and electrically connected to the TSV and TMV.

Abstract translation: 半导体器件具有安装在载体上的半导体管芯。 密封剂沉积在半导体管芯和载体上。 在半导体管芯和密封剂上形成绝缘层。 在安装到载体上时，通过绝缘层和半导体管芯形成多个第一通孔。 在将半导体管芯安装到载体上的同时，通过绝缘层和密封剂沿与第一通孔相同的方向形成多个第二通孔。 在第一通孔中沉积导电材料以形成导电TSV，并在第二通孔中形成导电TMV。 第一互连结构形成在绝缘层上并电连接到TSV和TMV。 载体被移除。 第二互连结构形成在半导体管芯和密封剂上并电连接到TSV和TMV。

公开(公告)号：US09202769B2

公开(公告)日：2015-12-01

申请号：US14509785

申请日：2014-10-08

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Il Kwon Shim

IPC: H01L21/44 ,  H01L23/367 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L21/56 ,  H01L23/552 ,  H01L21/683 ,  H01L23/538 ,  H01L23/42 ,  H01L23/498

CPC classification number: H01L23/367 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/19 ,  H01L2924/00012

Abstract: A semiconductor device has a first semiconductor die and an encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and encapsulant. A thermal interface material is formed over the first semiconductor die and encapsulant. A stiffening layer is formed over the first semiconductor die and an edge portion of the encapsulant. Alternatively, an insulating layer is formed adjacent to the first semiconductor die and a stiffening layer is formed over the insulating layer. The stiffening layer includes metal, ferrite, ceramic, or semiconductor material. A heat spreader is disposed over the first semiconductor die and a central portion of the encapsulant. Openings are formed in the heat spreader. A recess is formed in the heat spreader along an edge of the heat spreader. A coefficient of thermal expansion (CTE) of the stiffening layer is less than a CTE of the heat spreader.

Abstract translation: 半导体器件具有沉积在第一半导体管芯上的第一半导体管芯和密封剂。 在第一半导体管芯和密封剂上形成互连结构。 在第一半导体管芯和密封剂上形成热界面材料。 在第一半导体管芯上形成加强层和密封剂的边缘部分。 或者，与第一半导体管芯相邻地形成绝缘层，并且在绝缘层上形成加强层。 加强层包括金属，铁氧体，陶瓷或半导体材料。 散热器设置在第一半导体管芯上方和密封剂的中心部分。 开口形成在散热器中。 散热器沿着散热器的边缘形成凹部。 加强层的热膨胀系数（CTE）小于散热器的CTE。

公开(公告)号：US20150287708A1

公开(公告)日：2015-10-08

申请号：US14745203

申请日：2015-06-19

Applicant: STATS ChipPAC, LTD.

Inventor： Yaojian Lin ,  Kang Chen ,  Seung Wook Yoon

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/03 ,  H01L2224/03002 ,  H01L2224/03003 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0613 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2224/82005 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

Abstract translation: 半导体器件具有沉积在半导体管芯的第一表面上并且围绕半导体管芯的密封剂。 在半导体管芯的与第一表面相对的第二表面上形成第一绝缘层。 导电层形成在第一绝缘层上。 通过半导体管芯的覆盖区外的密封剂形成互连结构，并电连接到导电层。 第一绝缘层包括光学透明或半透明材料。 半导体管芯包括被配置为接收穿过第一绝缘层的外部刺激的传感器。 在半导体管芯的第一表面上形成第二绝缘层。 通过半导体管芯的覆盖区外的第一绝缘层形成导电通孔。 多个层叠的半导体器件通过互连结构电连接。

公开(公告)号：US09087930B2

公开(公告)日：2015-07-21

申请号：US14274599

申请日：2014-05-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。

公开(公告)号：US08994185B2

公开(公告)日：2015-03-31

申请号：US14043751

申请日：2013-10-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H05K1/18 ,  H01L23/31

CPC classification number: H01L24/06 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. A conductive micro via array is formed outside a footprint of the semiconductor die and over the semiconductor die and encapsulant. A first through-mold-hole (TMH) is formed including a step-through-hole structure through the encapsulant to expose the conductive micro via array. An insulating layer is formed over the semiconductor die and the encapsulant. A micro via array is formed through the insulating layer and outside the footprint of the semiconductor die. A conductive layer is formed over the insulating layer. A conductive ring is formed comprising the conductive micro via array. A second TMH is formed partially through the encapsulant to a recessed surface of the encapsulant. A third TMH is formed through the encapsulant and extending from the recessed surface of the encapsulant to the conductive micro via array.

Abstract translation: 半导体器件包括半导体管芯。 密封剂沉积在半导体管芯上。 导电微通孔阵列形成在半导体管芯的覆盖区之外并且在半导体管芯和密封剂之上。 形成第一通孔模具（TMH），其包括通过密封剂的通孔结构，以暴露导电微通孔阵列。 在半导体管芯和密封剂上形成绝缘层。 微通孔阵列通过绝缘层形成，并且在半导体管芯的覆盖区外部形成。 在绝缘层上形成导电层。 形成包括导电微通孔阵列的导电环。 第二TMH部分地通过密封剂形成到密封剂的凹陷表面。 通过密封剂形成第三TMH，并从密封剂的凹陷表面延伸到导电微通孔阵列。

公开(公告)号：US20150084213A1

公开(公告)日：2015-03-26

申请号：US14036193

申请日：2013-09-25

Applicant: STATS ChipPAC, Ltd.

Inventor： Kian Meng Heng ,  Hin Hwa Goh ,  Jose Alvin Caparas ,  Kang Chen ,  Seng Guan Chow ,  Yaojian Lin

IPC: H01L21/56 ,  H01L23/28

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/19 ,  H01L24/48 ,  H01L24/49 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.

Abstract translation: 半导体器件具有设置在衬底上方的加强层的衬底。 基板具有圆形或矩形形状。 多个半导体管芯设置在衬底的一部分上，同时留下没有半导体管芯的衬底的开放区域。 没有半导体管芯的基板的开放区域包括半导体管芯之间的中心区域或间隙位置。 半导体管芯围绕衬底的周边设置。 密封剂沉积在半导体管芯和衬底上。 去除衬底并在半导体管芯上方形成互连结构。 通过使没有半导体管芯的基板的预定区域离开，在去除衬底之后，半导体管芯的CTE与封装物的复合晶片的CTE之间的任何失配的翘曲效应降低。

公开(公告)号：US20150061124A1

公开(公告)日：2015-03-05

申请号：US14523556

申请日：2014-10-24

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/48 ,  H01L21/768 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract translation: 半导体器件具有形成在半导体晶片的有源表面上的保护层。 具有预先施加的保护层的半导体管芯从半导体晶片移动并安装在载体上。 载体上的半导体管芯和接触焊盘被封装。 载体被移除。 在预先施加的保护层和接触垫上形成第一绝缘层。 在第一绝缘层和预先施加的保护层中形成通孔以暴露半导体管芯上的互连部位。 在第一绝缘层上形成互连结构，与半导体管芯和接触焊盘上的互连部位电接触。 互连结构具有形成在第一绝缘层上的再分布层，形成在再分配层上的第二绝缘层和形成在与再分布层电接触的第二电介质上的凸块下金属化层。

公开(公告)号：US20150061123A1

公开(公告)日：2015-03-05

申请号：US14512614

申请日：2014-10-13

Applicant: STATS CHIPPAC, LTD.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/14 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13008 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/20101 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

Abstract translation: 半导体器件具有沉积在半导体管芯上的具有密封剂的半导体管芯。 在半导体管芯和密封剂上形成具有高拉伸强度和伸长率的第一绝缘层。 通过第一激光直接消融去除第一绝缘层的第一部分，以在第一绝缘层中形成多个开口。 这些开口部分地延伸穿过第一绝缘层或者进入密封剂。 通过第二激光直接烧蚀去除第一绝缘层的第二部分，以在第一绝缘层中形成多个沟槽。 在第一绝缘层的开口和沟槽中形成导电层。 在导电层上形成第二绝缘层。 通过第三激光直接烧蚀去除第二绝缘层的一部分。 在导电层上形成凸起。

公开(公告)号：US20140332986A1

公开(公告)日：2014-11-13

申请号：US14340187

申请日：2014-07-24

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Yaojian Lin

IPC: H01L21/56 ,  H01L21/68 ,  H01L23/28

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/565 ,  H01L21/68 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An adhesive material is deposited as a plurality of islands or bumps on the carrier or active surface of the semiconductor die. The adhesive layer can also be deposited as a continuous layer over the carrier or active surface of the die. The semiconductor die is mounted to the carrier. An encapsulant is deposited over the die and carrier. The adhesive material holds the semiconductor die in place to the carrier while depositing the encapsulant. An interconnect structure is formed over the active surface of the die. The interconnect structure is electrically connected to the bumps of the semiconductor die. The adhesive material can be removed prior to forming the interconnect structure, or the interconnect structure can be formed over the adhesive material.

Abstract translation: 半导体器件通过提供临时载体并提供具有在其有源表面上形成的多个凸起的半导体管芯制成。 粘合剂材料作为半导体管芯的载体或有源表面上的多个岛或凸起沉积。 粘合剂层也可以作为连续层沉积在模具的载体或活性表面上。 半导体管芯安装在载体上。 密封剂沉积在模具和载体上。 粘合剂材料在沉积密封剂的同时将半导体管芯保持在载体上。 在模具的有效表面上形成互连结构。 互连结构电连接到半导体管芯的凸点。 可以在形成互连结构之前去除粘合剂材料，或者可以在粘合剂材料上形成互连结构。