公开(公告)号：US09704943B2

公开(公告)日：2017-07-11

申请号：US14462490

申请日：2014-08-18

Applicant: XINTEC INC.

Inventor： Wei-Ming Lai ,  Yu-Wen Hu

IPC: H01L27/08 ,  H01L49/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/64 ,  H01L23/532

CPC classification number: H01L28/10 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/53238 ,  H01L23/645 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/11825 ,  H01L2224/11903 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1355 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/1206

Abstract: A manufacturing method of an inductor structure includes the following steps. A protection layer is formed on a substrate, such that bond pads of the substrate are respectively exposed form protection layer openings of the protection layer. A conductive layer is formed on the bond pads and the protection layer. A patterned first photoresist layer is formed on the conductive layer. Copper bumps are respectively formed on the conductive layer located in the first photoresist layer openings. A patterned second photoresist layer is formed on the first photoresist layer, such that at least one of the copper bumps is exposed through second photoresist layer opening and the corresponding first photoresist layer opening. A diffusion barrier layer and an oxidation barrier layer are formed on the copper bump. The first and second photoresist layers, and the conductive layer not covered by the copper bumps are removed.

公开(公告)号：US09685354B2

公开(公告)日：2017-06-20

申请号：US14676478

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Yi-Ming Chang

IPC: B26D1/09 ,  H01L21/67 ,  H01L21/683 ,  B26D7/18

CPC classification number: H01L21/67092 ,  B26D1/095 ,  B26D7/1863 ,  H01L21/6838 ,  Y10T83/0267 ,  Y10T225/10 ,  Y10T225/12 ,  Y10T225/364

Abstract: An embodiment of this invention provides a separation apparatus for separating a stacked article, such as a semiconductor chip package with sensing functions, comprising a substrate and a cap layer formed on the substrate. The separation apparatus comprises a vacuum nozzle head including a suction pad having a top surface and a bottom surface, a through hole penetrating the top surface and the bottom surface of the suction pad, and a hollow vacuum pipe connecting the through hole to a vacuum pump; a stage positing under the vacuum nozzle head and substantially aligning with the suction pad; a control means coupling to the vacuum nozzle head to lift upward or lower down the vacuum nozzle head; and a first cutter comprising a first cutting body and a first knife connecting to the first cutting body. The cap layer is pressed against by the bottom surface of the suction pad and sucked by the suction pad of the vacuum nozzle head after the vacuum pump begins to vacuum the air within the hollow vacuum pipe and the through hole. Then, the first cutter cuts into the interface between the substrate and the cap layer, and the cap lay is separated from the substrate by the suction force of the vacuum nozzle head and the lift force generated by the upward movement of the vacuum nozzle head.

公开(公告)号：US20170148844A1

公开(公告)日：2017-05-25

申请号：US15358852

申请日：2016-11-22

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Hsiao-Lan YEH ,  Chia-Sheng LIN ,  Yi-Ming CHANG ,  Po-Han LEE ,  Hui-Hsien WU ,  Jyun-Liang WU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chien-Min LIN

IPC: H01L27/146 ,  H01L21/48 ,  H01L21/67 ,  H01L23/18

CPC classification number: H01L27/14698 ,  H01L21/4803 ,  H01L21/67017 ,  H01L21/67132 ,  H01L23/18 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687

Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.

公开(公告)号：US09653422B2

公开(公告)日：2017-05-16

申请号：US14673657

申请日：2015-03-30

Applicant: XINTEC INC.

Inventor： Chia-Lun Shen ,  Yi-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/306 ,  H01L21/48

CPC classification number: H01L24/32 ,  H01L21/30604 ,  H01L21/48 ,  H01L21/78 ,  H01L24/05 ,  H01L24/09 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/8389 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/12042 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided.

公开(公告)号：US09640488B2

公开(公告)日：2017-05-02

申请号：US15008202

申请日：2016-01-27

Applicant: XINTEC INC.

Inventor： Yi-Min Lin ,  Yi-Ming Chang ,  Shu-Ming Chang ,  Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/78 ,  H01L29/06 ,  H01L23/00 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2223/5446 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/451 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

公开(公告)号：US09613904B2

公开(公告)日：2017-04-04

申请号：US15140289

申请日：2016-04-27

Applicant: XINTEC INC.

Inventor： Yu-Tung Chen ,  Chien-Min Lin ,  Chuan-Jin Shiu ,  Chih-Wei Ho ,  Yen-Shih Ho

IPC: H01L21/4763 ,  H01L21/44 ,  H01L23/04 ,  H01L23/52 ,  H01L23/528 ,  H01L21/027 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/5283 ,  H01L21/0271 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/0557

Abstract: A semiconductor structure includes a first substrate, a second substrate, a dam layer, a photoresist layer, and a conductive layer. The first substrate has a conductive pad. The second substrate has a through via, a sidewall surface surrounding the through via, a first surface, and a second surface opposite to the first surface. The through via penetrates through the first and second surfaces. The conductive pad is aligned with the through via. The dam layer is located between the first substrate and the second surface. The dam layer protrudes toward the through via. The photoresist layer is located on the first surface, the sidewall surface, the dam layer protruding toward the through via, and between the conductive pad and the dam layer protruding toward the through via. The conductive layer is located on the photoresist layer and the conductive pad.

公开(公告)号：US09601460B2

公开(公告)日：2017-03-21

申请号：US14618413

申请日：2015-02-10

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chia-Ming Cheng ,  Shu-Ming Chang ,  Tzu-Wen Tseng

IPC: H01L23/06 ,  H01L23/00 ,  H01L23/31 ,  H01L29/06 ,  H01L23/525

CPC classification number: H01L24/94 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/0657 ,  H01L2224/0224 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/06165 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/94 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess.

公开(公告)号：US20170076981A1

公开(公告)日：2017-03-16

申请号：US15364160

申请日：2016-11-29

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU ,  Ying-Nan WEN ,  Shih-Yi LEE ,  Ho-Yin YIU

IPC: H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L21/268 ,  H01L21/263

CPC classification number: H01L21/76898 ,  H01L21/2633 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/43 ,  H01L24/45 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/0233 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06135 ,  H01L2224/06182 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/432 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

Abstract translation: 芯片封装包括芯片，激光器停止器，隔离层，再分布层，绝缘层和导电结构。 芯片具有导电焊盘，第一表面和与第一表面相对的第二表面。 导电垫位于第一表面上。 第二表面具有第一通孔以暴露导电垫。 激光停止器位于导电垫上。 隔离层位于第二表面和第一通孔中。 隔离层具有与第二表面相对的第三表面。 隔离层和导电垫在一起具有第二通孔，使得激光阻挡件通过第二通孔露出。 再分配层位于第三表面，第二通孔的侧壁和激光停止器上。

公开(公告)号：US20170018590A1

公开(公告)日：2017-01-19

申请号：US15181291

申请日：2016-06-13

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括感测装置。 芯片封装还包括设置在感测装置上并电连接到感测装置的第一导电结构。 芯片封装还包括设置在感测装置上的芯片和第二导电结构。 该芯片包括集成电路器件。 第二导电结构位于芯片上并与集成电路器件和第一导电结构电连接。 此外，芯片封装包括覆盖感测装置和芯片的绝缘层。 绝缘层具有孔。 第一导电结构位于孔底部。 绝缘层的顶表面与第二导电结构的顶表面共面。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20160351608A1

公开(公告)日：2016-12-01

申请号：US15163625

申请日：2016-05-24

Applicant: XINTEC INC.

Inventor： Yu-Lung HUANG ,  Chi-Chang LIAO ,  Tsang-Yu LIU

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/14698 ,  H01L2224/16 ,  H01L2924/16235

Abstract: A chip package includes a substrate, a conductive layer and a plurality of thermal dissipation connections. The substrate includes a light-sensing region and has an upper surface and a lower surface opposite to each other. The conductive layer is disposed at the lower surface of the substrate and includes a light-shielding dummy conductive layer substantially aligned with the light-sensing region. The thermal dissipation connections are disposed beneath the lower surface of the substrate.

Abstract translation: 芯片封装包括衬底，导电层和多个散热连接。 基板包括感光区域，并且具有彼此相对的上表面和下表面。 导电层设置在基板的下表面，并且包括基本上与光感测区域对准的遮光虚拟导电层。 散热连接设置在基板的下表面之下。