公开(公告)号：US20070252274A1

公开(公告)日：2007-11-01

申请号：US11380215

申请日：2006-04-26

申请人： Timothy Daubenspeck ,  Mukta Farooq ,  Jeffrey Gambino ,  Christopher Muzzy ,  Kevin Petrarca ,  Wolfgang Sauter

发明人： Timothy Daubenspeck ,  Mukta Farooq ,  Jeffrey Gambino ,  Christopher Muzzy ,  Kevin Petrarca ,  Wolfgang Sauter

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05556 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/113 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00015 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.

摘要翻译： 一种用于在集成电路芯片上形成优选Pb-lead C4连接或具有球限制金属化的捕获焊盘的方法，其通过使用镶嵌工艺并且优选地在芯片中的Cu金属化和用于兼容性的球限制金属化中。 在两个实施例中，捕获垫形成在顶部绝缘层中，并且还用作芯片中金属化的最终级别。

公开(公告)号：US20070232049A1

公开(公告)日：2007-10-04

申请号：US11308539

申请日：2006-04-04

申请人： Daniel Edelstein ,  Mukta Farooq ,  Robert Hannon ,  Ian Melville

发明人： Daniel Edelstein ,  Mukta Farooq ,  Robert Hannon ,  Ian Melville

IPC分类号： H01L21/44

CPC分类号： H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03019 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/13116 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/01074 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01039 ,  H01L2224/05552

摘要： A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad in an upper level of a semiconductor wafer, forming an insulating stack over the terminal copper pad, and patterning and opening a terminal via within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer is formed and patterned over the top of the insulating stack, and the bottom cap layer over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack is deposited over the organic passivation layer and terminal copper pad, and a solder ball connection is formed on a patterned portion of the BLM stack.

摘要翻译： 用于远端（FBEOL）半导体器件形成的方法包括在半导体晶片的上层形成端子铜焊盘，在端子铜焊盘上形成绝缘堆叠，以及在端部铜焊盘的一部分内图案化和打开端子通孔 绝缘堆叠，以便留下保护端子铜焊盘的绝缘堆叠的底盖层。 在绝缘堆叠的顶部上形成并图案化有机钝化层，并且去除端子铜焊盘上的底盖层。 球限制冶金（BLM）堆叠沉积在有机钝化层和端子铜焊盘上，并且在BLM堆叠的图案化部分上形成焊球连接。

公开(公告)号：US20070222073A1

公开(公告)日：2007-09-27

申请号：US11308396

申请日：2006-03-21

申请人： Mukta Farooq ,  Jasvir Jaspal ,  William Landers ,  Thomas Lombardi ,  Hai Longworth ,  H. Pogge ,  Roger Quon

发明人： Mukta Farooq ,  Jasvir Jaspal ,  William Landers ,  Thomas Lombardi ,  Hai Longworth ,  H. Pogge ,  Roger Quon

IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L21/44

CPC分类号： H01L24/05 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/00014

摘要： A system and method comprises depositing a dielectric layer on a substrate and depositing a metal layer on the dielectric layer. The system and method further includes depositing a high temperature diffusion barrier metal cap on the metal layer. The system and method further includes depositing a second dielectric layer on the high temperature diffusion barrier metal cap and the first dielectric layer, and etching a via into the second dielectric layer, such that the high temperature diffusion barrier metal cap is exposed. The system and method further includes depositing an under bump metallurgy in the via, and forming a C4 ball on the under bump metallurgy layer.

摘要翻译： 一种系统和方法包括在基底上沉积电介质层并在介电层上沉积金属层。 该系统和方法还包括在金属层上沉积高温扩散阻挡金属帽。 该系统和方法还包括在高温扩散阻挡金属帽和第一电介质层上沉积第二电介质层，并将通孔蚀刻到第二电介质层中，使得暴露高温扩散阻挡金属帽。 该系统和方法还包括在通孔中沉积凸块下的冶金，并在凸块下金属层上形成C4球。

公开(公告)号：US20060231633A1

公开(公告)日：2006-10-19

申请号：US10907761

申请日：2005-04-14

申请人： Mukta Farooq ,  Benjamin Fasano ,  Jason Frankel ,  Harvey Hamel ,  Suresh Kadakia ,  David Long ,  Frank Pompeo ,  Sudipta Ray

发明人： Mukta Farooq ,  Benjamin Fasano ,  Jason Frankel ,  Harvey Hamel ,  Suresh Kadakia ,  David Long ,  Frank Pompeo ,  Sudipta Ray

IPC分类号： G06K19/06

CPC分类号： G06K19/07381 ,  H01L23/04 ,  H01L23/055 ,  H01L23/10 ,  H01L23/576 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/3011 ,  H05K1/0275 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/09263 ,  H05K2201/10151

摘要： A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

摘要翻译： 防干扰集成电路（IC）模块包括陶瓷芯片载体，附接到芯片载体的一个或多个集成电路芯片，以及附接到芯片载体的覆盖一个或多个集成电路芯片的盖结构。 在芯片载体和盖结构中形成导电栅格结构，该导电结构具有沿x方向，y方向和z方向设置的多条曲折线。 导电栅格结构被配置为检测穿透IC模块的尝试。

公开(公告)号：US20060040567A1

公开(公告)日：2006-02-23

申请号：US10711076

申请日：2004-08-20

申请人： William Bernier ,  Tien-Jen Cheng ,  Marie Cole ,  David Eichstadt ,  Mukta Farooq ,  John Fitzsimmons ,  Lewis Goldmann ,  John Knickerbocker ,  Tasha Lopez ,  David Welsh

发明人： William Bernier ,  Tien-Jen Cheng ,  Marie Cole ,  David Eichstadt ,  Mukta Farooq ,  John Fitzsimmons ,  Lewis Goldmann ,  John Knickerbocker ,  Tasha Lopez ,  David Welsh

IPC分类号： H05K1/00 ,  H01R12/00 ,  H01R13/42

CPC分类号： H01L21/563 ,  H01L23/3171 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13566 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01R43/0256 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/0401

摘要： Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.

摘要翻译： 公开了一种形成集成电路结构的方法，其在器件上形成无铅连接器，用可压缩膜围绕无铅连接器，将器件连接到载体（无铅连接器将器件电连接到载体上 ），并用绝缘底部填充物填充载体和装置之间的间隙。

公开(公告)号：US20050106059A1

公开(公告)日：2005-05-19

申请号：US10991581

申请日：2004-11-18

申请人： Mukta Farooq ,  Mario Interrante ,  William Sablinski

发明人： Mukta Farooq ,  Mario Interrante ,  William Sablinski

IPC分类号： B23K35/26 ,  C22C13/00 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H05K3/28 ,  H05K3/34

CPC分类号： H01L21/6835 ,  B23K35/262 ,  B23K2101/40 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81024 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/3463 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic package having a solder interconnect liquidus temperature hierarchy to limit the extent of the melting of the C4 solder interconnect during subsequent second level join/assembly and rework operations. The solder hierarchy employs the use of off-eutectic solder alloys of Sn/Ag and Sn/Cu with a higher liquidus temperature for the C4 first level solder interconnections, and a lower liquidus temperature alloy for the second level interconnections. When the second level chip carrier to PCB join/assembly operations occur, the chip to chip carrier C4 interconnections do not melt completely. They continue to have a certain fraction of solids, and a lower fraction of liquids, than a fully molten alloy. This provides reduced expansion of the solder join and consequently lower stresses on the C4 interconnect.

公开(公告)号：US20070290345A1

公开(公告)日：2007-12-20

申请号：US11847776

申请日：2007-08-30

申请人： Lawrence Clevenger ,  Mukta Farooq ,  Louis Hsu ,  William Landers ,  Donna Zupanski-Nielsen ,  Carl Radens ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Mukta Farooq ,  Louis Hsu ,  William Landers ,  Donna Zupanski-Nielsen ,  Carl Radens ,  Chih-Chao Yang

IPC分类号： H01L23/488 ,  H01L21/34

CPC分类号： H05K3/3436 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/12 ,  H01L24/17 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/49109 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K2201/094 ,  H05K2201/09736 ,  H05K2201/09845 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.

摘要翻译： 一种电结构和方法，包括电和机械地连接到第二衬底的第一衬底。 第一基板包括第一导电焊盘和第二导电焊盘。 第二基板包括第三导电焊盘，第四导电焊盘和第一导电部件。 第四导电焊盘包括与第一导电构件的高度不同的高度。 导电构件电连接和机械地连接到第四导电垫。 第一焊球将第一导电焊盘连接到第三导电焊盘。 第一焊球包括第一直径。 第二焊球将第二导电焊盘连接到第一导电构件。 第二焊球包括第二直径。 第一直径大于所述第二直径。

公开(公告)号：US20070228117A1

公开(公告)日：2007-10-04

申请号：US11759298

申请日：2007-06-07

申请人： Mukta Farooq ,  Charles Goldsmith

发明人： Mukta Farooq ,  Charles Goldsmith

IPC分类号： B23K31/02

CPC分类号： B23K3/0638 ,  B23K2101/40 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10992 ,  Y02P70/613 ,  Y10T29/49149

摘要： Methods of forming and assemblies having hybrid interconnection grid arrays composed of a homogenous mixture of Pb-free solder joints and Pb-containing solder paste on corresponding sites of a printed board. The aligned Pb-free solder joints and Pb-containing solders are heated to a temperature above a melting point of the Pb-free solder joint for a sufficient time to allow complete melting of both the Pb-free solder joints and Pb-containing solder paste and the homogenous mixing thereof during assembly. These molten materials mix together such that the Pb from the Pb-containing solder disperses throughout substantially the entire Pb-free solder joint for complete homogenization of the molten materials to form the homogenous hybrid interconnect structures of the invention.

摘要翻译： 具有混合互连栅格阵列的形成和组装方法，其由印刷电路板的相应位置上的无铅焊点和含Pb焊膏的均匀混合物组成。 将排列的无铅焊点和含Pb焊料加热到无铅焊点的熔点以上的温度足够的时间，以使无铅焊点和含Pb焊膏完全熔化 并在组装期间均匀混合。 这些熔融材料混合在一起，使得来自含Pb焊料的Pb分散在基本上整个无铅焊料接头处，以使熔融材料完全均化，形成本发明的均匀混合互连结构。

公开(公告)号：US20070178625A1

公开(公告)日：2007-08-02

申请号：US11307291

申请日：2006-01-31

申请人： David Danovitch ,  Mukta Farooq ,  Michael Gaynes

发明人： David Danovitch ,  Mukta Farooq ,  Michael Gaynes

IPC分类号： H01L21/00

CPC分类号： H01L21/6835 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/742 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2224/05599

摘要： Composite interconnect structure forming methods using injection molded solder are disclosed. The methods provide a mold having at least one opening formed therein with each opening including a member of a material dissimilar to a solder to be used to fill the opening, and then fill the remainder of each opening with solder to form the composite interconnect structure. The resulting composite interconnect structure can be leveraged to achieve a much larger variety of composite structures than exhibited by the prior art. For example, the material may be chosen to be more electrically conductive than the solder portion, more electromigration-resistant than the solder portion and/or more fatigue-resistant than the solder portion. In one embodiment, the composite interconnect structure can include an optical structure, or plastic or ceramic material. The optical structure provides radiation propagation and/or amplification between waveguides in the substrate and device, and the plastic material provides fatigue-resistance.

摘要翻译： 公开了使用注射成型焊料的复合互连结构形成方法。 该方法提供了一种具有形成在其中的至少一个开口的模具，每个开口包括与用于填充开口的焊料不同的材料的构件，然后用焊料填充每个开口的剩余部分以形成复合互连结构。 可以利用所得到的复合互连结构来实现比现有技术表现出的更大的复合结构。 例如，材料可以被选择为比焊料部分更具导电性，比焊料部分更具有电迁移性和/或比焊料部分更耐疲劳性。 在一个实施例中，复合互连结构可以包括光学结构，或塑料或陶瓷材料。 该光学结构在衬底和器件中的波导之间提供辐射传播和/或放大，并且塑料材料提供耐疲劳性。

公开(公告)号：US20060172565A1

公开(公告)日：2006-08-03

申请号：US10906111

申请日：2005-02-03

申请人： William Bernier ,  David Eichstadt ,  Mukta Farooq ,  John Knickerbocker

发明人： William Bernier ,  David Eichstadt ,  Mukta Farooq ,  John Knickerbocker

IPC分类号： H01R12/00

CPC分类号： H01L24/13 ,  G01R1/06716 ,  G01R1/07314 ,  G01R3/00 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/81 ,  H01L2221/68377 ,  H01L2224/11003 ,  H01L2224/114 ,  H01L2224/11505 ,  H01L2224/116 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1318 ,  H01L2224/13184 ,  H01L2224/81205 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8384 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K3/06 ,  H05K3/3436 ,  H05K2201/10242 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/49204 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method of forming compliant electrical contacts includes patterning a conductive layer into an array of compliant members. The array of compliant members is then positioned to be in contact with electrical connection pads on an integrated circuit wafer and the compliant members are joined to the pads. Then, the supporting layer that supported the compliant members is removed to leave the compliant members connected to the pads.

摘要翻译： 形成顺应性电触头的方法包括将导电层图案化为顺应构件阵列。 然后将顺应构件阵列定位成与集成电路晶片上的电连接焊盘接触，并且柔性构件连接到焊盘。 然后，移除支撑柔顺构件的支撑层，以使与柔性构件连接的衬垫离开。