公开(公告)号：US09099567B2

公开(公告)日：2015-08-04

申请号：US14089744

申请日：2013-11-25

Applicant: Lakshminarayan Viswanathan ,  L. M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

Inventor： Lakshminarayan Viswanathan ,  L. M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/00 ,  H05K1/14 ,  B23K20/02 ,  B23K35/02 ,  B23K20/24 ,  B23K20/16 ,  B23K20/10 ,  B23K20/00

CPC classification number: H01L24/73 ,  B23K20/002 ,  B23K20/023 ,  B23K20/10 ,  B23K20/16 ,  B23K20/24 ,  B23K35/0244 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8348 ,  H01L2224/83484 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01322 ,  H01L2924/04541 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/1306 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/15793 ,  H01L2924/181 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2201/2072 ,  H05K2203/1322 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.

Abstract translation: 将半导体管芯附接到衬底的方法的实施例包括使用插入的管芯附着材料将管芯的底表面放置在衬底的顶表面上。 该方法还包括使半导体管芯的顶表面和衬底的顶表面与保形结构接触，该保形结构包括非固体，压力传递材料，并向保形结构施加压力。 压力通过非固体的压力传递材料传递到半导体管芯的顶表面。 该方法还包括在施加压力的同时，将组件暴露于足以使管芯附着材料烧结的温度。 在将管芯置于衬底上之前，可以在衬底的顶表面和/或半导体管芯的底表面上形成导电的机械锁定特征。

公开(公告)号：US08753983B2

公开(公告)日：2014-06-17

申请号：US12683961

申请日：2010-01-07

Applicant: Jin-Wook Jang ,  Lalgudi M. Mahalingam ,  Audel A. Sanchez ,  Lakshminarayan Viswanathan

Inventor： Jin-Wook Jang ,  Lalgudi M. Mahalingam ,  Audel A. Sanchez ,  Lakshminarayan Viswanathan

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L23/373 ,  H01L23/057 ,  H01L23/3731 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/838 ,  H01L2224/83805 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0489 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method includes providing a silicon-containing die and providing a heat sink having a palladium layer over a first surface of the heat sink. A first gold layer is located over one of a first surface of the die or the palladium layer. The silicon-containing die is bonded to the heat sink, where bonding includes joining the silicon-containing die and the heat sink such that the first gold layer and the palladium layer are between the first surface of the silicon-containing die and the first surface of the heat sink, and heating the first gold layer and the palladium layer to form a die attach layer between the first surface of the silicon-containing die and the first surface of the heat sink, the die attach layer comprising a gold interface layer having a plurality of intermetallic precipitates, each of the plurality of intermetallic precipitates comprising palladium, gold, and silicon.

Abstract translation: 一种方法包括提供含硅模头并且在散热器的第一表面上提供具有钯层的散热器。 第一金层位于管芯的第一表面或钯层之一上。 所述含硅芯片与所述散热器接合，其中，所述接合包括将所述含硅芯片与所述散热器接合，使得所述第一金层和所述钯层位于所述含硅模具的所述第一表面和所述第一表面之间 并且加热所述第一金层和所述钯层以在所述含硅芯片的所述第一表面和所述散热器的所述第一表面之间形成管芯附着层，所述管芯附着层包括金界面层，所述金界面层具有 多个金属间化合物沉淀物，多个金属间析出物中的每一个包括钯，金和硅。

公开(公告)号：US20090023248A1

公开(公告)日：2009-01-22

申请号：US12242622

申请日：2008-09-30

Applicant: David F. Abdo ,  Alexander J. Elliott ,  Lakshminarayan Viswanathan

Inventor： David F. Abdo ,  Alexander J. Elliott ,  Lakshminarayan Viswanathan

IPC: H01L21/56 ,  H01L23/495

CPC classification number: H01L23/4334 ,  H01L21/565 ,  H01L23/49541 ,  H01L23/66 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of packaging a semiconductor die includes the steps of providing a flange (110), coupling one or more active die (341) to the flange with a lead-free die attach material (350), staking a leadframe (120) to the flange after coupling the one or more active die to the flange, electrically interconnecting the one or more active die and the leadframe with an interconnect structure (470), and applying a plastic material (130) over the flange, the one or more active die, the leadframe, and the interconnect structure.

Abstract translation: 封装半导体管芯的方法包括以下步骤：提供凸缘（110），将一个或多个有源管芯（341）与无铅管芯附接材料（350）连接到法兰上，将引线框架（120）铆接到 将所述一个或多个有源管芯连接到所述凸缘之后，使所述一个或多个有源管芯和所述引线框架与互连结构（470）电互连，以及在所述凸缘上施加塑料材料（130），所述一个或多个有源管芯 ，引线框架和互连结构。

公开(公告)号：US07445967B2

公开(公告)日：2008-11-04

申请号：US11336368

申请日：2006-01-20

Applicant: David F. Abdo ,  Alexander J. Elliott ,  Lakshminarayan Viswanathan

Inventor： David F. Abdo ,  Alexander J. Elliott ,  Lakshminarayan Viswanathan

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC classification number: H01L23/4334 ,  H01L21/565 ,  H01L23/49541 ,  H01L23/66 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of packaging a semiconductor die includes the steps of providing a flange (110), coupling one or more active die (341) to the flange with a lead-free die attach material (350), staking a leadframe (120) to the flange after coupling the one or more active die to the flange, electrically interconnecting the one or more active die and the leadframe with an interconnect structure (470), and applying a plastic material (130) over the flange, the one or more active die, the leadframe, and the interconnect structure.

Abstract translation: 封装半导体管芯的方法包括以下步骤：提供凸缘（110），将一个或多个有源管芯（341）与无铅管芯附接材料（350）连接到法兰上，将引线框架（120）铆接到 将所述一个或多个有源管芯连接到所述凸缘之后，使所述一个或多个有源管芯和所述引线框架与互连结构（470）电互连，以及在所述凸缘上施加塑料材料（130），所述一个或多个有源管芯 ，引线框架和互连结构。

公开(公告)号：US07429790B2

公开(公告)日：2008-09-30

申请号：US11257783

申请日：2005-10-24

Applicant: Brian W. Condie ,  Lakshminarayan Viswanathan ,  Richard W. Wetz

Inventor： Brian W. Condie ,  Lakshminarayan Viswanathan ,  Richard W. Wetz

IPC: H01L23/10

CPC classification number: H01L23/13 ,  H01L23/10 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/01025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor structure (100) includes a substrate (110) having a first surface (111) with a mold lock feature (101). The semiconductor structure also includes a semiconductor chip (120) located over the first surface of the substrate. The semiconductor structure further includes an electrical isolator structure (340) located over the first surface of the substrate. The electrical isolator structure includes an electrical lead (341, 342) and an electrically insulative element (343) molded to the electrical lead. An optional portion (444) of the electrical isolator structure is located in the mold lock feature. The semiconductor structure additionally includes an adhesive element (450) located between and coupling the electrical isolator structure and the first surface of the substrate.

Abstract translation: 半导体结构（100）包括具有模具锁定特征（101）的第一表面（111）的基板（110）。 半导体结构还包括位于衬底的第一表面上方的半导体芯片（120）。 半导体结构还包括位于衬底的第一表面上方的电隔离器结构（340）。 电隔离器结构包括电引线（341,342）和模制到电引线上的电绝缘元件（343）。 电隔离器结构的可选部分（444）位于模具锁定特征中。 半导体结构还包括位于电隔离器结构和衬底的第一表面之间的耦合的粘合元件（450）。

公开(公告)号：US20070172990A1

公开(公告)日：2007-07-26

申请号：US11336368

申请日：2006-01-20

Applicant: David Abdo ,  Alexander Elliott ,  Lakshminarayan Viswanathan

Inventor： David Abdo ,  Alexander Elliott ,  Lakshminarayan Viswanathan

IPC: H01L21/00

CPC classification number: H01L23/4334 ,  H01L21/565 ,  H01L23/49541 ,  H01L23/66 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of packaging a semiconductor die includes the steps of providing a flange (110), coupling one or more active die (341) to the flange with a lead-free die attach material (350), staking a leadframe (120) to the flange after coupling the one or more active die to the flange, electrically interconnecting the one or more active die and the leadframe with an interconnect structure (470), and applying a plastic material (130) over the flange, the one or more active die, the leadframe, and the interconnect structure.

Abstract translation: 封装半导体管芯的方法包括以下步骤：提供凸缘（110），将一个或多个有源管芯（341）与无铅管芯附接材料（350）连接到法兰上，将引线框架（120）铆接到 将所述一个或多个有源管芯连接到所述凸缘之后，使所述一个或多个有源管芯和所述引线框架与互连结构（470）电互连，以及在所述凸缘上施加塑料材料（130），所述一个或多个有源管芯 ，引线框架和互连结构。

公开(公告)号：US09673162B2

公开(公告)日：2017-06-06

申请号：US13613979

申请日：2012-09-13

Applicant: Lakshminarayan Viswanathan ,  Scott M. Hayes ,  Scott D. Marshall ,  Mahesh K. Shah

Inventor： Lakshminarayan Viswanathan ,  Scott M. Hayes ,  Scott D. Marshall ,  Mahesh K. Shah

IPC: H01L29/10 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/24 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method and apparatus for incorporation of high power device dies into smaller system packages by embedding metal “coins” having high thermal conductivity into package substrates, or printed circuit boards, and coupling the power device dies onto the metal coins is provided. In one embodiment, the power device die can be attached to an already embedded metal coin in the package substrate or PCB. The power device die can be directly coupled to the embedded metal coin or the power device die can be attached to a metallic interposer which is then bonded to the embedded metal coin. In another embodiment, the die can be attached to the metal coin and then the PCB or package substrate can be assembled to incorporate the copper coin. Active dies are coupled to each other either through wire bonds or other passive components, or using a built-up interconnect.

公开(公告)号：US09362198B2

公开(公告)日：2016-06-07

申请号：US14249538

申请日：2014-04-10

Applicant: Lakshminarayan Viswanathan ,  Bruce M. Green ,  Darrell G. Hill ,  L M Mahalingam

Inventor： Lakshminarayan Viswanathan ,  Bruce M. Green ,  Darrell G. Hill ,  L M Mahalingam

IPC: H01L31/102 ,  H01L23/367 ,  H01L21/762 ,  H01L21/3205 ,  H01L21/04 ,  H01L21/28 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20

CPC classification number: H01L23/373 ,  H01L21/042 ,  H01L21/0475 ,  H01L21/28 ,  H01L21/32051 ,  H01L21/762 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/04026 ,  H01L2224/29026 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.

Abstract translation: 半导体器件的实施例包括半导体衬底，其包括主体衬底和上表面，有源区域，半导体衬底中的由凹陷表面局部限定的衬底开口，以及设置在半导体衬底上的导热层 其在有源区域内在凹入表面和半导体衬底的一部分之间延伸。 制造半导体器件的方法包括限定有源区域，在有源区域中的沟道上形成栅电极，在栅电极的相对侧上的有源区域中形成源电极和漏电极，蚀刻栅电极的衬底开口 所述半导体衬底由所述凹陷表面部分地限定，并且在所述半导体衬底上沉积导热层，所述导热层在所述沟道上在所述凹陷表面和所述半导体衬底的一部分之间延伸。

公开(公告)号：US20160099199A1

公开(公告)日：2016-04-07

申请号：US14508645

申请日：2014-10-07

Applicant: Lakshminarayan Viswanathan ,  Jaynal A. Molla

Inventor： Lakshminarayan Viswanathan ,  Jaynal A. Molla

IPC: H01L23/495

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/741 ,  H01L24/743 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/03436 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03505 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05551 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05794 ,  H01L2224/05839 ,  H01L2224/05844 ,  H01L2224/05847 ,  H01L2224/05855 ,  H01L2224/05864 ,  H01L2224/05887 ,  H01L2224/0589 ,  H01L2224/05893 ,  H01L2224/27002 ,  H01L2224/2731 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/27438 ,  H01L2224/27505 ,  H01L2224/29006 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29015 ,  H01L2224/29017 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29084 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/29117 ,  H01L2224/29118 ,  H01L2224/2912 ,  H01L2224/29124 ,  H01L2224/29138 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2918 ,  H01L2224/29184 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/296 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/741 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83815 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/1016 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1421 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/3512 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/01015 ,  H01L2924/01048 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01028 ,  H01L2924/01027 ,  H01L2924/01026 ,  H01L2224/03 ,  H01L2224/05099 ,  H01L2924/01006 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2221/68304 ,  H01L21/304 ,  H01L21/78 ,  H01L2224/83 ,  H01L2924/0781 ,  H01L2924/00 ,  H01L2224/034 ,  H01L2221/68368 ,  H01L2224/274

Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

Abstract translation: 电子器件包括具有下表面的半导体管芯，位于半导体管芯的下表面下方的烧结金属层，在烧结金属层下面的导热流动层，以及位于导热流动层下面的导热基底。

公开(公告)号：US20150249021A1

公开(公告)日：2015-09-03

申请号：US14204338

申请日：2014-03-11

Applicant: Audel A. Sanchez ,  Fernando A. Santos ,  Lakshminarayan Viswanathan

Inventor： Audel A. Sanchez ,  Fernando A. Santos ,  Lakshminarayan Viswanathan

IPC: H01L21/56 ,  H01L23/495 ,  H01L23/00 ,  H01L23/367 ,  H01L21/768

CPC classification number: H01L21/56 ,  H01L21/76895 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/20755 ,  H01L2924/00012

Abstract: A method for a packaged leadless semiconductor device including a heat sink flange to which semiconductor dies are coupled using a high temperature die attach process. The semiconductor device further includes a frame structure pre-formed with bent terminal pads. The frame structure is combined with the flange so that a lower surface of the flange and a lower section of each terminal pad are in coplanar alignment, and so that an upper section of each terminal pad overlies the flange. Interconnects interconnect the die with the upper section of the terminal pad. An encapsulant encases the frame structure, flange, die, and interconnects with the lower section of each terminal pad and the lower surface of the flange remaining exposed from the encapsulant.

Abstract translation: 一种包装无铅半导体器件的方法，其包括使用高温管芯附接工艺将半导体管芯耦合到其上的散热器法兰。 半导体器件还包括预先形成有弯曲的端子焊盘的框架结构。 框架结构与凸缘组合，使得凸缘的下表面和每个端子垫的下部共面对准，并且使得每个端子垫的上部覆盖在凸缘上。 互连器件将管芯与端子焊盘的上部部分互连。 密封剂将框架结构，法兰，管芯和每个端子衬垫的下部和凸缘的下表面保持暴露于密封剂的相互连接。