公开(公告)号：US09660181B2

公开(公告)日：2017-05-23

申请号：US13994715

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

IPC: H01L43/12 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

公开(公告)号：US09252111B2

公开(公告)日：2016-02-02

申请号：US14625579

申请日：2015-02-18

Applicant: Intel Corporation

Inventor： Kevin J. Lee

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L21/768 ,  H01L21/683

CPC classification number: H01L24/11 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/5384 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11001 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/27436 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/11848 ,  H01L21/304

Abstract: A structure and method of handling a device wafer during through-silicon via (TSV) processing are described in which a device wafer is bonded to a temporary support substrate with a permanent thermosetting material. Upon removal of the temporary support substrate a planar frontside bonding surface including a reflowed solder bump and the permanent thermosetting material is exposed.

Abstract translation: 描述了在贯穿硅通孔（TSV）处理期间处理器件晶片的结构和方法，其中器件晶片通过永久性热固性材料结合到临时支撑衬底。 在移除临时支撑基板时，露出包括回流焊料凸块和永久性热固性材料的平面前沿接合表面。

公开(公告)号：US11037896B2

公开(公告)日：2021-06-15

申请号：US16216881

申请日：2018-12-11

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Ruchir Saraswat ,  Uwe Zillmann ,  Nicholas P. Cowley ,  Richard J. Goldman

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/66 ,  G06F1/16 ,  H01F27/28 ,  H01L23/64 ,  H03H7/42 ,  H03H9/64 ,  H01L23/525

Abstract: Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the backside, the one or more passive planar devices formed in the RDL.

公开(公告)号：US10790263B2

公开(公告)日：2020-09-29

申请号：US16287915

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Kevin J. Lee

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L49/02 ,  H01L23/14 ,  H01L23/525

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, the IC die may include a semiconductor substrate, a plurality of active components disposed on a first side of the semiconductor substrate, and a plurality of passive components disposed on a second side of the semiconductor substrate. In embodiments the second side may be disposed opposite the first side. The passive components may, in some embodiments, include capacitors and/or resistors while the active components may, in some embodiments, include transistors. Other embodiments may be described and/or claimed.

公开(公告)号：US10455308B2

公开(公告)日：2019-10-22

申请号：US15502495

申请日：2014-09-17

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Ruchir Saraswat ,  Uwe Zillmann ,  Valluri Bob Rao ,  Tor Lund-Larsen ,  Nicholas P. Cowley

IPC: H04R19/04 ,  H04R1/04 ,  B81B7/02 ,  H01L23/00 ,  H01L21/683 ,  H01L23/48 ,  B81C1/00 ,  H01L21/768 ,  H04R1/40 ,  H04R19/00

Abstract: Embodiments of the present disclosure describe a die with integrated microphone device using through-silicon vias (TSVs) and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a semiconductor substrate having a first side and a second side disposed opposite to the first side, an interconnect layer formed on the first side of the semiconductor substrate, a through-silicon via (TSV) formed through the semiconductor substrate and configured to route electrical signals between the first side of the semiconductor substrate and the second side of the semiconductor substrate, and a microphone device formed on the second side of the semiconductor substrate and electrically coupled with the TSV. Other embodiments may be described and/or claimed.

公开(公告)号：US09911689B2

公开(公告)日：2018-03-06

申请号：US15038623

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Kevin J. Lee ,  Ruchir Saraswat ,  Uwe Zillmann ,  Nicholas P. Cowley ,  Andre Schaefer ,  Rinkle Jain ,  Guido Droege

IPC: H01L21/48 ,  H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L25/065 ,  H01L23/48 ,  H01L21/822 ,  H01L23/492 ,  H01L23/498 ,  H01L27/06

CPC classification number: H01L23/5223 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/4875 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/492 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L25/0657 ,  H01L27/0629 ,  H01L28/90 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).

公开(公告)号：US09721886B2

公开(公告)日：2017-08-01

申请号：US14778667

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Hiten Kothari ,  Wayne M. Lytle

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/525 ,  H01L23/48

CPC classification number: H01L23/528 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/525 ,  H01L23/53238 ,  H01L2224/1182 ,  H01L2224/13565

Abstract: An embodiment includes a semiconductor apparatus comprising: a redistribution layer (RDL) including a patterned RDL line having two RDL sidewalls, the RDL comprising a material selected from the group comprising Cu and Au; protective sidewalls directly contacting the two RDL sidewalls; a seed layer including the material; and a barrier layer; wherein (a) the RDL line has a RDL line width orthogonal to and extending between the two RDL sidewalls, and (b) the seed and barrier layers each include a width parallel to and wider than the RDL line width. Other embodiments are described herein.

公开(公告)号：US09716066B2

公开(公告)日：2017-07-25

申请号：US14779022

申请日：2013-06-29

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  James Y. Jeong ,  Hsiao-Kang Chang ,  John Muirhead ,  Adwait Telang ,  Puneesh Puri ,  Jiho Kang ,  Nitin M. Patel

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L23/5384 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/116 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16145 ,  H01L2924/13091 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014

Abstract: A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

公开(公告)号：US09852964B2

公开(公告)日：2017-12-26

申请号：US15116435

申请日：2014-03-24

Applicant: INTEL CORPORATION

Inventor： Kevin J. Lee

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L21/288 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/288 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76873 ,  H01L21/76898 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/02 ,  H01L24/05 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2225/06544

Abstract: Techniques are disclosed for forming a through-body-via (TBV) in a semiconductor die. In accordance with some embodiments, a TBV provided using the disclosed techniques includes a polymer-based barrier layer and an electrically conductive seed layer formed by applying an electrically conductive ink directly to the barrier layer and then curing it in situ. In some embodiments, after curing, the resultant seed layer may be a thin, substantially conformal, electrically conductive metal film over which the TBV interconnect metal can be deposited. In some example cases, a polyimide, parylene, benzocyclobutene (BCB), and/or polypropylene carbonate (PPC) barrier layer and an ink containing copper (Cu) and/or silver (Ag), of nanoparticle-based or metal complex-based formulation, may be used in forming the TBV. In some instances, the disclosed techniques may be used to address poor step coverage, low run rate, and/or high cost issues associated with existing physical vapor deposition (PVD)-based far-back-end-of-line (FBEOL) processes.

公开(公告)号：US09530740B2

公开(公告)日：2016-12-27

申请号：US14836828

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Christopher M. Pelto ,  Hiten Kothari ,  Seshu V. Sattiraju ,  Hang-Shing Ma

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/29 ,  H01L23/31 ,  H01L23/528 ,  H01L21/683

CPC classification number: H01L23/5384 ,  H01L21/6835 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5286 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/6835 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17106 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/186 ,  H01L2924/381 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.