公开(公告)号：US11557541B2

公开(公告)日：2023-01-17

申请号：US16235879

申请日：2018-12-28

申请人： Intel Corporation

发明人： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Robert Sankman ,  Ravindranath V. Mahajan ,  Debendra Mallik ,  Ram S. Viswanath ,  Sandeep B. Sane ,  Sriram Srinivasan ,  Rajat Agarwal ,  Aravind Dasu ,  Scott Weber ,  Ravi Gutala

IPC分类号： H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

摘要： Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US11049798B2

公开(公告)日：2021-06-29

申请号：US16457336

申请日：2019-06-28

申请人： Intel Corporation

发明人： Aditya S. Vaidya ,  Ravindranath V. Mahajan ,  Digvijay A. Raorane ,  Paul R. Start

IPC分类号： H01L23/48 ,  H01L23/49 ,  H01L21/76 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H01L25/065

摘要： An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US20190287956A1

公开(公告)日：2019-09-19

申请号：US16464665

申请日：2016-12-30

申请人： Intel Corporation

发明人： Digvijay A. Raorane ,  Ravindranath V. Mahajan

IPC分类号： H01L25/18 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768

摘要： An apparatus is provided comprising: a substrate; a die having a first side and a second side, wherein the die is mounted on the substrate such that the first side of the die faces the substrate, and wherein at least a portion of the first side of the die is removed to form a recess in the die; and a component, wherein at least a part of the component is disposed within the recess in the first die.

公开(公告)号：US20190006264A1

公开(公告)日：2019-01-03

申请号：US15640406

申请日：2017-06-30

申请人： Intel Corporation

发明人： Aditya S. Vaidya ,  Ravindranath V. Mahajan ,  Digvijay A. Raorane ,  Paul R. Start

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/09 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/16225

摘要： An apparatus comprising: a substrate having a first side opposing a second side, and comprises a first conductive layer disposed on the first side of the package substrate, and a second conductive layer disposed between the first side and the second side of the package substrate, the substrate having dielectric material disposed between the first conductive layer and the second conductive layer; and at least one at least one bridge die disposed within the substrate, the at least one bridge die having a first side opposing a second side, and comprising a plurality of vias extending from the first side to the second side of the at least one bridge die, wherein the second conductive layer disposed between the first and second sides of the substrate is coupled to the plurality of vias extending from the first side of the at least one bridge die to the second side of the at least one bridge die.

公开(公告)号：US09847308B2

公开(公告)日：2017-12-19

申请号：US14566185

申请日：2014-12-10

申请人： Intel Corporation

发明人： Rajasekaran Swaminathan ,  Ravindranath V. Mahajan

IPC分类号： H01L23/00 ,  H01L23/498 ,  H05K3/34

CPC分类号： H01L24/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/742 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/1132 ,  H01L2224/11418 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13311 ,  H01L2224/13316 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13387 ,  H01L2224/13411 ,  H01L2224/13447 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/75264 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81222 ,  H01L2224/81409 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/3494 ,  H05K2201/0341 ,  H05K2201/083 ,  H05K2201/10674 ,  H05K2203/104 ,  Y02P70/613 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/05381 ,  H01L2924/053 ,  H01L2924/0532 ,  H01L2924/01056

摘要： The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.

公开(公告)号：US20170301625A1

公开(公告)日：2017-10-19

申请号：US15636117

申请日：2017-06-28

申请人： Intel Corporation

发明人： Ravindranath V. Mahajan ,  Christopher J. Nelson ,  Omkar G. Karhade ,  Feras Eid ,  Nitin A. Deshpande ,  Shawna M. Liff

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065

CPC分类号： H01L23/5381 ,  H01L21/563 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/24145 ,  H01L2224/24245 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/0665

摘要： Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

公开(公告)号：US09775763B2

公开(公告)日：2017-10-03

申请号：US13719336

申请日：2012-12-19

申请人： Intel Corporation

发明人： Aleksandar Aleksov ,  Brian S. Doyle ,  Ravindranath V. Mahajan

IPC分类号： A61H1/02 ,  A61H3/00

CPC分类号： A61H1/024 ,  A61H1/0244 ,  A61H1/0266 ,  A61H1/0277 ,  A61H1/0281 ,  A61H1/0285 ,  A61H1/0288 ,  A61H1/0296 ,  A61H3/00 ,  A61H2201/1609 ,  A61H2201/1614 ,  A61H2201/1628 ,  A61H2201/1635 ,  A61H2201/164 ,  A61H2201/165 ,  A61H2201/5002 ,  A61H2201/501 ,  A61H2201/5097 ,  A61H2230/605

摘要： Exoskeleton technology is described herein. Such technology includes but is not limited to exoskeletons, exoskeleton controllers, methods for controlling an exoskeleton, and combinations thereof. The exoskeleton technology may facilitate, enhance, and/or supplant the natural mobility of a user via a combination of sensor elements, processing/control elements, and actuating elements. User movement may be elicited by electrical stimulation of the user's muscles, actuation of one or more mechanical components, or a combination thereof. In some embodiments, the exoskeleton technology may adjust in response to measured inputs, such as motions or electrical signals produced by a user. In this way, the exoskeleton technology may interpret known inputs and learn new inputs, which may lead to a more seamless user experience.

公开(公告)号：US09323327B2

公开(公告)日：2016-04-26

申请号：US13726078

申请日：2012-12-22

申请人： Intel Corporation

发明人： Aleksandar Aleksov ,  Ravindranath V. Mahajan ,  Brian S. Doyle

IPC分类号： G06F3/01 ,  G06F3/041 ,  G06F3/0481

CPC分类号： G06F3/016 ,  G06F3/014 ,  G06F3/0412 ,  G06F3/04812 ,  G06F3/0488

摘要： A system and method for providing tactile feedback in a user interface. The system includes a tactile feedback assembly configured to communicate with a user interface of an electronic device. The tactile feedback assembly is configured to provide mechanical and/or nerve stimulation to a user during user interaction (e.g. navigation, input of data, etc.) of the user interface. The mechanical and/or nerve stimulation is configured to provide a user with tactile sensation (in the form of the sense of touch) in response to user interaction with the user interface, including, but not limited to, sense of texture and sense of pressure.

摘要翻译： 一种用于在用户界面中提供触觉反馈的系统和方法。 该系统包括被配置为与电子设备的用户界面通信的触觉反馈组件。 触觉反馈组件被配置为在用户界面的用户交互（例如，导航，数据输入等）期间向用户提供机械和/或神经刺激。 机械和/或神经刺激被配置为响应于用户与用户界面的交互而向用户提供触觉（以触觉的形式），包括但不限于纹理感和压力感 。

公开(公告)号：US11832419B2

公开(公告)日：2023-11-28

申请号：US16723865

申请日：2019-12-20

申请人： Intel Corporation

发明人： Nicholas Neal ,  Nicholas S. Haehn ,  Je-Young Chang ,  Kyle Arrington ,  Aaron McCann ,  Edvin Cetegen ,  Ravindranath V. Mahajan ,  Robert L. Sankman ,  Ken P. Hackenberg ,  Sergio A. Chan Arguedas

IPC分类号： H05K7/20 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

CPC分类号： H05K7/20309 ,  H01L23/3672 ,  H01L23/49816 ,  H01L24/14

摘要： Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.

公开(公告)号：US11756889B2

公开(公告)日：2023-09-12

申请号：US16534027

申请日：2019-08-07

申请人： Intel Corporation

发明人： Sanka Ganesan ,  Kevin McCarthy ,  Leigh M. Tribolet ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Robert L. Sankman

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

CPC分类号： H01L23/5381 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/20 ,  H01L24/80 ,  H01L2221/68354 ,  H01L2221/68372 ,  H01L2224/08225 ,  H01L2224/214 ,  H01L2224/80006 ,  H01L2224/80894 ,  H01L2924/0105 ,  H01L2924/01029 ,  H01L2924/05442

摘要： Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.