公开(公告)号：US20060103483A1

公开(公告)日：2006-05-18

申请号：US11186859

申请日：2005-07-22

Applicant: Sung-Mao Wu ,  Chi-Tsung Chiu ,  Chih-Pin Hung

Inventor： Sung-Mao Wu ,  Chi-Tsung Chiu ,  Chih-Pin Hung

IPC: H03H5/02

CPC classification number: H05K1/0216 ,  H01G4/236 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09509

Abstract: An inductor and capacitor implemented with build-up vias. The inductor and capacitor comprise a conductor plane, a dielectric layer, an inductor/capacitor inducing build-up via and a conductor layer. There is a conducting material in the inductor/capacitor inducing build-up via and a fist end thereof is in contact with the conductor plane. The length of the inductor inducing build-up via is larger than one fourth of a signal wavelength while the length of the conductor inducing build-up via is smaller than one fourth of a signal wavelength.

Abstract translation: 用积层通孔实现的电感和电容器。 电感器和电容器包括导体平面，电介质层，电感器/电容器，用于引导积聚通孔和导体层。 在电感器/电容器中存在导电材料，其导致积聚通孔，并且其第一端与导体平面接触。 感应电感通孔的电感长度大于信号波长的四分之一，而导体积聚通孔的导体长度小于信号波长的四分之一。

公开(公告)号：US20060084288A1

公开(公告)日：2006-04-20

申请号：US10969369

申请日：2004-10-19

Applicant: Ping Chuang ,  Li-Sen Chen ,  Chien-Yu Hsu

Inventor： Ping Chuang ,  Li-Sen Chen ,  Chien-Yu Hsu

IPC: H01R12/00

CPC classification number: H05K3/326 ,  H01R12/52 ,  H01R13/2414 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2201/10378

Abstract: An LGA connector is used to interconnect an LGA package and a printed circuit board. The LGA connector includes an elastomeric body with a plurality of through-holes. Metal films are formed on inner walls of through-holes and splay out around the mouths of their upper and lower openings. The metal films are formed by vacuum metallization, sputtering, chemical plating, electrical plating or PVD. The through-holes have a funnel-like shape to absorb external stresses and redirect the stress to shrink the through-hole diameters. Moreover, the metal films' elastic deformation is larger than conventional metal conductive fillers so as to improve reliability.

Abstract translation: LGA连接器用于连接LGA封装和印刷电路板。 LGA连接器包括具有多个通孔的弹性体。 金属膜形成在通孔的内壁上，并在其上部和下部开口的嘴部周围张开。 金属膜通过真空金属化，溅射，化学镀，电镀或PVD形成。 通孔具有漏斗形形状以吸收外部应力并且重定向应力以收缩通孔直径。 此外，金属膜的弹性变形大于常规金属导电填料，从而提高可靠性。

公开(公告)号：US07030815B2

公开(公告)日：2006-04-18

申请号：US10936286

申请日：2004-09-08

Applicant: Gregory J. Dunn ,  Jeffrey M. Petsinger ,  William R. Ziemer

Inventor： Gregory J. Dunn ,  Jeffrey M. Petsinger ,  William R. Ziemer

IPC: H01Q1/38

CPC classification number: H05K1/16 ,  H01Q1/22 ,  H01Q1/38 ,  H01Q9/0407 ,  H01Q23/00 ,  H05K1/024 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/09454 ,  H05K2201/09509

Abstract: An integrated patch antenna and electronics assembly (300) comprises an antenna dielectric layer (305), a ground plane layer (310) disposed on a first side of the antenna dielectric layer, a printed circuit dielectric layer (315) disposed on the ground plane layer opposite the antenna dielectric layer, a patterned conductive metal foil layer (320) on a component surface (323) of the assembly (300), and a conductive metal foil antenna patch (325) disposed on a second side of the antenna dielectric layer that is in a patch side (391) of the assembly. In some embodiments, a plated through hole (330) couples the antenna patch to the patterned conductive metal foil layer. In some embodiments, there are one or more printed circuit dielectric layers (316, 341, 346, 351) disposed over the antenna patch on the antenna patch side of the assembly. In some embodiments, pairs of printed circuit dielectric layers ([315, 316], [340, 341], [345, 346], [350, 351]) are formed simultaneously on each side of the assembly.

公开(公告)号：US20060073639A1

公开(公告)日：2006-04-06

申请号：US11285347

申请日：2005-11-23

Applicant: Masahiro Sunohara ,  Kei Murayama ,  Naohiro Mashino ,  Mitsutoshi Higashi

Inventor： Masahiro Sunohara ,  Kei Murayama ,  Naohiro Mashino ,  Mitsutoshi Higashi

IPC: H01L21/50

CPC classification number: H05K1/185 ,  H01L21/78 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/05548 ,  H01L2224/16237 ,  H01L2224/24051 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K3/4602 ,  H05K2201/09509 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171

Abstract: There is provided a electronic parts packaging structure that includes a mounted body on which an electronic parts is mounted, the electronic parts having a connection pad, which has an etching stopper film (a copper film, a gold film, a silver film, or a conductive past film) as an uppermost film, and mounted on the mounted body to direct the connection pad upward, an interlayer insulating film for covering the electronic parts, a via hole formed in the insulating film on the connection pad of the electronic parts, and a wiring pattern connected to the connection pad via the via hole.

公开(公告)号：US20060044504A1

公开(公告)日：2006-03-02

申请号：US11211020

申请日：2005-08-24

Applicant: Kazuyuki Yamada ,  Yasuhito Aruga

Inventor： Kazuyuki Yamada ,  Yasuhito Aruga

IPC: G02F1/1345

CPC classification number: G02F1/13454 ,  G02F1/13452 ,  G02F1/13458 ,  H01L2224/16225 ,  H01L2924/15192 ,  H05K1/117 ,  H05K3/361 ,  H05K3/4644 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09709

Abstract: An electro-optical device includes a substrate having a display region; and an extending region extending from the display region. The extending region is provided with wiring lines, and at least some wiring lines, which are disposed to be adjacent to each other, are correspondingly disposed in a plurality of different layers.

公开(公告)号：US06990734B2

公开(公告)日：2006-01-31

申请号：US10263006

申请日：2002-10-02

Applicant: Jeffrey A. Underwood ,  John K. Arledge ,  Thomas J. Swirbel ,  Joaquin Barreto

Inventor： Jeffrey A. Underwood ,  John K. Arledge ,  Thomas J. Swirbel ,  Joaquin Barreto

IPC: H05K3/34

CPC classification number: H05K1/0218 ,  H01L2223/6622 ,  H05K1/0221 ,  H05K1/0222 ,  H05K1/113 ,  H05K3/4644 ,  H05K9/0039 ,  H05K2201/0715 ,  H05K2201/09036 ,  H05K2201/09509 ,  H05K2201/09809 ,  H05K2201/09972 ,  H05K2201/09981 ,  H05K2201/10553 ,  H05K2201/10969 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: Methods for forming a metal shield on a printed circuit board (10) include depositing a first layer of metal (41) on a substrate (22) of the printed circuit board (10), depositing a first layer of dielectric material (42) on the first layer of metal (41), printing one or more circuits (21, 21′) on the first dielectric layer (42), depositing a second layer of dielectric material (43) over the one or more printed circuits (21, 21′), forming a trench-like opening (44) in the two layers of dielectric material (42, 43) surrounding the one or more printed circuits (21, 21′) so that the metal of the first layer (41) is exposed by the trench-like opening (44), depositing a second layer of metal (27) on the second layer of dielectric material (43) such that the second layer of metal (27) plates the trench-like opening (44) and makes electrical contact with the first metal layer (41).

Abstract translation: 在印刷电路板（10）上形成金属屏蔽的方法包括在印刷电路板（10）的基板（22）上沉积第一金属层（41），将第一层介电材料（42）沉积在 所述第一金属层（41），在所述第一介电层（42）上印刷一个或多个电路（21,21'），在所述一个或多个印刷电路（21,21）上沉积第二介电材料层 '），在围绕所述一个或多个印刷电路（21,21'）的两层介电材料（42,43）中形成沟槽状开口（44），使得第一层（41）的金属暴露 通过所述沟槽状开口（44），在所述第二介电材料层（43）上沉积第二金属层（27），使得所述第二金属层（27）平坦化所述沟槽状开口（44）并使 与第一金属层（41）电接触。

公开(公告)号：US20050269685A1

公开(公告)日：2005-12-08

申请号：US10863700

申请日：2004-06-07

Applicant: Stephen Chung ,  Jungle Lee ,  Shinn-Juh Lay ,  Randy Wu ,  Huey-Ru Chang ,  Yu-Mei Cheng

Inventor： Stephen Chung ,  Jungle Lee ,  Shinn-Juh Lay ,  Randy Wu ,  Huey-Ru Chang ,  Yu-Mei Cheng

IPC: H01L23/498 ,  H01L23/50 ,  H01L31/119 ,  H05K1/11 ,  H05K1/16 ,  H05K3/46

CPC classification number: H05K1/162 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09663 ,  H05K2201/10674

Abstract: A unitary buried array capacitor and microelectronic structures incorporating such capacitors are disclosed. A unitary buried array capacitor can be formed by a top layer of electrode, a middle layer of dielectric, and a bottom layer of electrode. A first electrode lead, a second electrode lead and at least one interconnect line pass through the three layers while only the first electrode lead making electrical contact with the top layer of electrode and only the second electrode lead making electrical contact with the bottom electrode.

Abstract translation: 公开了一种整体埋地阵列电容器和结合这种电容器的微电子结构。 单一埋地阵列电容器可以由电极的顶层，电介质的中间层和电极的底层形成。 第一电极引线，第二电极引线和至少一个互连线穿过三层，而只有第一电极引线与电极的顶层电接触，并且仅第二电极引线与底部电极电接触。

公开(公告)号：US06969912B2

公开(公告)日：2005-11-29

申请号：US10713804

申请日：2003-11-14

Applicant: Uei-Ming Jow ,  Pei-Shen Wei ,  Ching-Liang Weng ,  Chun-Kun Wu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

Inventor： Uei-Ming Jow ,  Pei-Shen Wei ,  Ching-Liang Weng ,  Chun-Kun Wu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

IPC: H01L21/4763 ,  H01L23/053 ,  H01L23/48 ,  H05K1/02 ,  H05K1/16 ,  H05K3/46

CPC classification number: H05K1/162 ,  H05K1/0218 ,  H05K1/0219 ,  H05K3/4602 ,  H05K2201/0723 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09672

Abstract: An embedded microelectronic capacitor incorporating at least one ground shielding layer is provided which includes an upper ground shielding layer that has an aperture therethrough; an electrode plate positioned spaced-apart from the upper ground shielding layer that has a via extending upwardly away from the electrode plate through the aperture in the upper ground shielding layer providing electrical communication to the electrode plate without shorting to the upper ground shielding layer; a middle ground shielding layer positioned in the same plane of the electrode plate, surrounding while spaced-apart from the electrode plate at a predetermined distance; a lower ground shielding layer positioned spaced-apart from the electrode plate in an opposing relationship to the upper ground shielding layer; and a dielectric material embedding the upper ground shielding layer; the middle ground shielding layer and the lower ground shielding layer.

Abstract translation: 提供了包括至少一个接地屏蔽层的嵌入式微电子电容器，其包括具有穿过其中的孔的上接地屏蔽层; 与所述上接地屏蔽层间隔开的电极板，所述电极板具有通过所述上接地屏蔽层中的孔向上远离所述电极板延伸的通孔，所述通孔提供与所述电极板的电连通而不与所述上接地屏蔽层短路; 位于电极板的同一平面中的中间屏蔽层，以与预定距离的电极板隔开间隔开; 与所述上接地屏蔽层相对的位置与所述电极板隔开定位的下接地屏蔽层; 以及嵌入上接地屏蔽层的电介质材料; 中间接地屏蔽层和下部接地屏蔽层。

公开(公告)号：US20050208789A1

公开(公告)日：2005-09-22

申请号：US11109656

申请日：2005-04-20

Applicant: Takehiro Shirai ,  Masayuki Iwase

Inventor： Takehiro Shirai ,  Masayuki Iwase

IPC: G02B6/38 ,  G02B6/42 ,  H01L23/24 ,  H01L23/498 ,  H01R12/00 ,  H05K1/05 ,  H05K3/44

CPC classification number: G02B6/4201 ,  G02B6/3885 ,  G02B6/4277 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/24 ,  H01L23/49861 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0219 ,  H05K1/056 ,  H05K3/06 ,  H05K3/44 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09754 ,  H05K2201/10121 ,  H05K2203/0323 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A printed wiring board includes a plurality of conductor plates that includes at least one conductor plate that is used as a lead for electrical connection with an external circuit, the conductor plates being separated spatially from one another; an insulating layer formed on or across the conductor plates or both on and across the conductor plates; and a plurality of wiring patterns formed on the insulating layer. At least one of the conductor plates is electrically connected with at least one of the wiring patterns through a via-hole.

Abstract translation: 印刷布线板包括多个导体板，其包括至少一个导体板，该导体板用作与外部电路电连接的引线，导体板彼此空间分离; 在导体板上或横跨导体板上形成绝缘层，或者两者在导体板上并跨过导体板; 以及形成在所述绝缘层上的多个布线图案。 至少一个导体板通过通孔与至少一个布线图形电连接。

公开(公告)号：US20050205516A1

公开(公告)日：2005-09-22

申请号：US11073615

申请日：2005-03-08

Applicant: Hiroshi Sugimoto ,  Tatsuya Ohtaka ,  Shigeharu Takahagi

Inventor： Hiroshi Sugimoto ,  Tatsuya Ohtaka ,  Shigeharu Takahagi

IPC: B23K26/00 ,  B23K26/38 ,  B23K101/42 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46 ,  H01B13/00

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05026 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09527 ,  H01L2224/05599

Abstract: A wiring board with microstrip structure has: a first conductor layer that is provided with conductor wirings to be connected to a semiconductor chip in its external terminal (bonding pad); a second conductor layer that is provided with a conductor pattern connected through a via to a ground wiring, for supplying a power supply of ground potential to the semiconductor chip; and a third conductor layer that is provided with a power supply terminal connected through a via to a power supply wiring for supplying an operation power supply of a potential other than the ground potential to the semiconductor chip, a signal terminal connected through a via to a signal wiring for transmitting an electric signal, and a ground terminal connected through a via to the conductor pattern in the second conductor layer.

Abstract translation: 具有微带结构的布线板具有：第一导体层，其在其外部端子（接合焊盘）中设置有与半导体芯片连接的导体布线; 第二导体层，其设置有通过通孔连接到接地布线的导体图案，用于向半导体芯片提供接地电位; 以及第三导体层，其具有通过通孔连接到电源布线的电源端子，用于向半导体芯片提供除了地电位以外的电位的操作电源，通过通孔连接到 用于发送电信号的信号线路，以及通过通孔连接到第二导体层中的导体图案的接地端子。