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    METHODS AND STRUCTURE FOR CARRIER-LESS THIN WAFER HANDLING
    226.
    发明申请
    METHODS AND STRUCTURE FOR CARRIER-LESS THIN WAFER HANDLING 有权
    无载波干扰处理的方法和结构

    公开(公告)号：US20150255345A1

    公开(公告)日：2015-09-10

    申请号：US14722672

    申请日：2015-05-27

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Michael Newman ,  Charles G. Woychik ,  Terrence Caskey

    IPC: H01L21/768 ,  H01L23/00 ,  H01L21/3105 ,  H01L21/78 ,  H01L21/683

    CPC classification number: H01L21/76898 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/481 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

    Abstract: Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.

    Abstract translation: 本文公开了形成微电子组件的方法以及所得到的结构和装置。 在一个实施例中，形成微电子组件的方法包括去除在衬底的表面的部分处暴露的材料，以形成经处理的衬底，该衬底具有多个由处理衬底的整体支撑部分分离的薄化部分，该部分厚度大于厚度 减薄部分中的至少一些薄化部分包括在薄壁部分的厚度方向上延伸并在表面露出的多个导电互连件; 以及去除衬底的支撑部分以将衬底切割成多个单独的薄化部分，至少一些单独的变薄部分，包括互连。

    Z-CONNECTION USING ELECTROLESS PLATING
    227.
    发明申请
    Z-CONNECTION USING ELECTROLESS PLATING 有权
    使用电镀镀层的Z型连接

    公开(公告)号：US20150243644A1

    公开(公告)日：2015-08-27

    申请号：US14709011

    申请日：2015-05-11

    Applicant: Invensas Corporation

    Inventor： Belgacem Haba ,  Cyprian Emeka Uzoh

    IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00

    CPC classification number: H01L25/50 ,  H01L21/50 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/53209 ,  H01L24/83 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/808 ,  H01L2224/8385 ,  H01L2224/8389 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2924/15311 ,  H01L2924/2064

    Abstract: In one embodiment, an assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact being electrically connected with the terminal; a first element having a first surface facing the first surface of the substrate and having a first conductor at the first surface and a second conductor at a second surface, an interconnect structure extending through the first element electrically connecting the first and second conductors; an adhesive layer bonding the first surfaces of the first element and the substrate, at least portions of the first conductor and the substrate conductor being disposed beyond an edge of the adhesive layer; and a continuous electroless plated metal region extending between the first conductor and the substrate conductor.

    Abstract translation: 在一个实施例中，组件包括具有衬底导体的衬底和在第一表面处的触点和在第二表面处的端子，用于将组件与组件外部的部件电互连，衬底导体或触点中的至少一个 与终端电连接; 第一元件，其具有面向基板的第一表面的第一表面，并且在第一表面具有第一导体，在第二表面具有第二导体，互连结构，延伸穿过第一元件，电连接第一和第二导体; 粘接所述第一元件和所述基板的所述第一表面的粘合剂层，所述第一导体和所述基板导体的至少一部分设置在所述粘合剂层的边缘之外; 以及在第一导体和衬底导体之间延伸的连续化学镀金属区域。

    VIA IN SUBSTRATE WITH DEPOSITED LAYER
    229.
    发明申请
    VIA IN SUBSTRATE WITH DEPOSITED LAYER 有权
    通过具有沉积层的基板

    公开(公告)号：US20150140815A1

    公开(公告)日：2015-05-21

    申请号：US14605654

    申请日：2015-01-26

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh

    IPC: H01L21/768

    CPC classification number: H01L21/76805 ,  H01L21/02107 ,  H01L21/486 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/49827 ,  H01L2221/1057 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough interior surface. A smoothing layer such as a polysilicon layer is applied over the interior surfaces of the openings. The smoothing layer presents a surface smoother than the original interior surface. An insulating layer is formed over the smoothing layer or formed from the smoothing layer, and a conductive element such as a metal is formed in the opening. In a variant, a glass-forming material such as BPSG is applied in the opening. The glass-forming material is reflowed to form a glassy insulating layer which presents a smooth surface. The interface between the metal conductive element and the insulating or glassy layer is smooth, which improves mechanical and electrical properties.

    Abstract translation: 诸如小直径通孔的开口通过高蚀刻速率工艺形成在诸如单晶硅芯片或晶片的半导体衬底中，这使得开口具有粗糙的内表面。 诸如多晶硅层的平滑层被施加在开口的内表面上。 平滑层呈现比原始内表面更平滑的表面。 在平滑层上形成绝缘层或由平滑层形成，并且在开口中形成诸如金属的导电元件。 在一个变型中，在开口中施加诸如BPSG的玻璃形成材料。 玻璃形成材料被回流以形成呈现光滑表面的玻璃状绝缘层。 金属导电元件与绝缘层或玻璃层之间的界面是光滑的，这提高了机械和电气性能。

    CAVITIES CONTAINING MULTI-WIRING STRUCTURES AND DEVICES
    230.
    发明申请
    CAVITIES CONTAINING MULTI-WIRING STRUCTURES AND DEVICES 有权
    包含多层结构和设备的CAVITIES

    公开(公告)号：US20150101858A1

    公开(公告)日：2015-04-16

    申请号：US14573461

    申请日：2014-12-17

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh ,  Craig Mitchell ,  Belgacem Haba ,  Ilyas Mohammed

    IPC: H05K1/02 ,  H05K1/11 ,  H01R12/71

    CPC classification number: H05K1/0271 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/714 ,  H05K1/114 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09645 ,  H05K2201/10378 ,  H05K2203/0242 ,  H05K2203/025 ,  Y10T29/49165 ,  H01L2924/00

    Abstract: A method is disclosed for making an interconnection component. The steps include forming a mask layer covering a first opening in a sheet-like element that has first and second opposed surfaces; forming a plurality of mask openings in the mask layer, wherein the first opening and a portion of the first surface are partly aligned with each mask opening; and forming electrical conductors on spaced apart portions of the first surface and on spaced apart portions of the interior surface within the first opening which are exposed by the mask openings. The element may consist essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. Each conductor may extend along an axial direction of the first opening and the first conductors may be fully separated from one another within the first opening.

    Abstract translation: 公开了一种制造互连部件的方法。 所述步骤包括在具有第一和第二相对表面的片状元件中形成覆盖第一开口的掩模层; 在所述掩模层中形成多个掩模开口，其中所述第一开口和所述第一表面的一部分与每个掩模开口部分对准; 以及在所述第一开口中的所述第一表面的间隔开的部分和所述第一开口内的所述内表面的间隔开的部分上形成电导体，所述部分被所述掩模开口暴露。 元件可以基本上由热膨胀系数小于10ppm /℃的材料组成。 每个导体可以沿着第一开口的轴向方向延伸，并且第一导体可以在第一开口内彼此完全分离。

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