公开(公告)号：US06579744B1

公开(公告)日：2003-06-17

申请号：US09819077

申请日：2000-07-05

Applicant: Tongbi Jiang

Inventor： Tongbi Jiang

IPC: H01L2144

CPC classification number: H01L24/83 ,  H01L24/16 ,  H01L24/28 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13016 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29499 ,  H01L2224/81141 ,  H01L2224/81903 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/14 ,  H01R4/04 ,  H05K1/111 ,  H05K3/323 ,  H05K2201/09745 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The present invention includes electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive. In one embodiment, an electrical interconnection configured to electrically couple a first substrate and a second substrate includes: a bond pad of the first substrate having a male configuration; and a bond pad of the second substrate having a female configuration, the bond pad of the second substrate being configured to mate with the bond pad of the first substrate during electrical connection of the bond pads of the first substrate and the second substrate. A method of conducting electricity according to the present invention includes providing first and second bond pads individually defining a planar dimension; coupling the first and second bond pads at an interface having a surface area greater than the area of the planar dimension; and conducting electricity between the first and second bond pads following the coupling.

公开(公告)号：US06573461B2

公开(公告)日：2003-06-03

申请号：US09957373

申请日：2001-09-20

Applicant: Glen E. Roeters ,  Frank E. Mantz

Inventor： Glen E. Roeters ,  Frank E. Mantz

IPC: H01R1204

CPC classification number: H05K3/462 ,  H01L2224/13019 ,  H01L2224/16057 ,  H01L2924/01322 ,  H05K3/321 ,  H05K3/4069 ,  H05K2201/096 ,  H05K2201/09745 ,  H05K2201/10378 ,  H01L2924/00

Abstract: A retaining ring interconnect. A retaining ring is formed on a perimeter of a pad on each of two adjoining surfaces of two PCB substrates. A conductive paste is applied between the pads on the two adjoining surfaces. The retaining rings are aligned and facing with each other. By performing a heat compression process, the retaining rings are connected to encompass the conductive paste. A eutectic bond is thus formed to bond the two PCB substrates.

公开(公告)号：US20030058629A1

公开(公告)日：2003-03-27

申请号：US10253295

申请日：2002-09-24

Inventor： Taro Hirai ,  Gorou Ikegami

IPC: H05K007/10 ,  H05K007/12

CPC classification number: H01L24/97 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19043 ,  H05K1/113 ,  H05K1/116 ,  H05K3/064 ,  H05K3/184 ,  H05K3/423 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2203/0369 ,  H05K2203/0574 ,  Y10T29/49155 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wiring substrate for used in a small electronic component. The wiring substrate comprises: an insulating substrate; and a conductive land portion which is formed on a first surface of the insulating substrate and on which an electronic element is to be mounted via conductive adhesive to electrically couple an electrode of the electronic element with the conductive land portion. The thickness of the peripheral portion of the conductive land portion which surrounds the electronic element is thicker than that of the central portion of the conductive land portion. The insulating substrate may also have a conductive land portion which is formed on a second surface of the insulating substrate and which is electrically coupled with the conductive land portion formed on the first surface of the insulating substrate via a through hole penetrating through the insulating substrate.

Abstract translation: 一种用于小型电子部件的布线基板。 布线基板包括：绝缘基板; 以及形成在所述绝缘基板的第一表面上并且通过导电粘合剂安装电子元件以将所述电子元件的电极与所述导电接地部分电耦合的导电接地部分。 围绕电子元件的导电接地部分的周边部分的厚度比导电接地部分的中心部分的厚度厚。 绝缘基板还可以具有形成在绝缘基板的第二表面上的导电接合部，并且通过穿过绝缘基板的通孔与形成在绝缘基板的第一表面上的导电接合部电耦合。

公开(公告)号：US20030051907A1

公开(公告)日：2003-03-20

申请号：US09957373

申请日：2001-09-20

Inventor： Glen E. Roeters ,  Frank E. Mantz

IPC: H05K001/16

CPC classification number: H05K3/462 ,  H01L2224/13019 ,  H01L2224/16057 ,  H01L2924/01322 ,  H05K3/321 ,  H05K3/4069 ,  H05K2201/096 ,  H05K2201/09745 ,  H05K2201/10378 ,  H01L2924/00

Abstract: A retaining ring interconnect. A retaining ring is formed on a perimeter of a pad on each of two adjoining surfaces of two PCB substrates. A conductive paste is applied between the pads on the two adjoining surfaces. The retaining rings are aligned and facing with each other. By performing a heat compression process, the retaining rings are connected to encompass the conductive paste. A eutectic bond is thus formed to bond the two PCB substrates.

Abstract translation: 保持环互连。 在两个PCB基板的两个邻接表面中的每一个上的垫的周边上形成有保持环。 导电膏被施加在两个相邻表面上的垫之间。 保持环对齐并相互面对。 通过进行热压缩工艺，保持环被连接以包围导电浆料。 因此形成共晶键以结合两个PCB基板。

公开(公告)号：US06501661B1

公开(公告)日：2002-12-31

申请号：US10027443

申请日：2001-12-21

Applicant: Kevin D. Moore ,  Thomas P. Gall ,  Jeffrey Lord

Inventor： Kevin D. Moore ,  Thomas P. Gall ,  Jeffrey Lord

IPC: H05K500

CPC classification number: H05K1/0278 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/09063 ,  H05K2201/09109 ,  H05K2201/09745 ,  H05K2203/302

Abstract: An electronic control unit (ECU) includes a flexible circuit substrate having a first partition interconnected to a third partition by a second, flexible partition. The electronic control unit further includes a rigidizer having a first partition interconnected to a third partition by a second partition. When the ECU is twice folded, the second, flexible partition of the circuit substrate assumes an approximate ‘U’-shape, resulting in a reduced cracking and splitting rate than the prior art. In various embodiments of the present invention, the assumption of a ‘U’-shaped fold in the second, flexible partition of the circuit substrate is facilitated by multiple apertures in a second rigidizer partition, by a depression in a second rigidizer partition, or by non-slidably affixing a first circuit substrate partition to a first rigidizer partition via a first adhesive and non-slidably affixing a third circuit substrate partition to a third rigidizer partition via a second adhesive.

Abstract translation: 电子控制单元（ECU）包括柔性电路基板，该柔性电路基板具有通过第二柔性隔板互连到第三隔板的第一隔板。 电子控制单元还包括刚性化器，其具有通过第二分隔件互连到第三分隔件的第一分隔件。 当ECU被两次折叠时，电路基板的第二柔性隔板呈现近似的“U”形，导致与现有技术相比降低的开裂和分裂速率。在本发明的各种实施例中，假设a “在第二刚性分隔器中的多个孔口，通过在第二刚性化器隔板中的凹陷，或通过不可滑动地将第一电路衬底隔板固定到第一刚性分隔件 经由第一粘合剂的刚性分隔件，并且通过第二粘合剂将第三电路基板隔板不可滑动地附接到第三刚性分隔件。

公开(公告)号：US20020194731A1

公开(公告)日：2002-12-26

申请号：US10219173

申请日：2002-08-13

Applicant: Altera Corporation

Inventor： Sidney Larry Anderson

IPC: H05K003/34 ,  H01R009/00 ,  H01K003/10

CPC classification number: H01L24/32 ,  H01L21/4853 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/16237 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/8547 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/112 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/041 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/0133 ,  H01L2924/01049 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/13111 ,  H01L2224/05552 ,  H01L2224/45015 ,  H01L2224/45099

Abstract: An integrated circuit package is provided with a ball landing area having a conductive structure for interlocking a conductive ball to the ball pad. The conductive structure improves the attachment strength between an integrated circuit package and an printed circuit board. In an exemplary embodiment, the locking structure is a conductive material added to the surface of the ball pad to provide a nonplanar interface, such as a dome or a step, which interlocks the conductive ball to the ball pad. The improved package construction increases the area of contact, moves the shear plane to a higher and larger portion on the conductive ball, and/or prevents a crack from propagating along a flat plane across the ball joint. This package construction maintains the small size of the ball land areas and the package, increases the life of the integrated circuit package, while offsetting the problem of package warpage.

Abstract translation: 集成电路封装设置有具有用于将导电球与球垫互锁的导电结构的球着陆区域。 导电结构提高了集成电路封装和印刷电路板之间的附着强度。 在示例性实施例中，锁定结构是添加到球垫表面的导电材料，以提供将导电球与球垫互锁的非平面界面，例如圆顶或台阶。 改进的包装结构增加了接触面积，将剪切平面移动到导电球上的更大和更大的部分，和/或防止裂纹沿着穿过球窝接头的平面传播。 该封装结构保持了球形区域和封装的小尺寸，增加了集成电路封装的使用寿命，同时抵消了封装翘曲的问题。

公开(公告)号：US20020145207A1

公开(公告)日：2002-10-10

申请号：US09517345

申请日：2000-03-02

Inventor： Sidney Larry Anderson ,  Jon Long ,  Donald S. Fritz

IPC: H01L023/28

CPC classification number: H01L24/32 ,  H01L21/4853 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/16237 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/112 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/041 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: An integrated circuit package is constructed to potential reduce stress and damage to an integrated circuit die. A rigid transition medium (220) is attached using adhesive layers (215, 42) and interfaces between a tape carrier (260) and the integrated circuit die (210). The integrated circuit package prevents damage such as die cracks and also enhances the service life of the packaged integrated circuit part.

Abstract translation: 构建集成电路封装，以减少对集成电路管芯的压力和损坏。 使用粘合剂层（215,42）和带状载体（260）和集成电路管芯（210）之间的界面附接刚性过渡介质（220）。 集成电路封装可防止诸如裸片裂纹的损坏，并且还可提高封装集成电路部件的使用寿命。

公开(公告)号：US06400234B1

公开(公告)日：2002-06-04

申请号：US09500995

申请日：2000-02-09

Applicant: Hideyuki Ohhashi ,  Yukihiro Tahara ,  Moriyasu Miyazaki

Inventor： Hideyuki Ohhashi ,  Yukihiro Tahara ,  Moriyasu Miyazaki

IPC: H01P502

CPC classification number: H01P3/088 ,  H01P5/085 ,  H01R12/523 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/0272 ,  H05K3/0061 ,  H05K3/429 ,  H05K2201/0379 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/09745 ,  H05K2201/09809 ,  H05K2201/10356

Abstract: A reflection characteristic in a high frequency region at a feeding point into a strip line is improved and the assembly of a strip line feeding apparatus facilitated by the method and apparatus herein. The strip line includes a strip line pattern on a surface of a first dielectric substrate having a ground conductor pattern disposed on the opposite surface thereof, and a second ground conductor pattern disposed on a surface of a second dielectric substrate. A serial high impedance portion is disposed at an area near the tip portion of the strip line pattern. The high impedance portion includes a portion of the strip line pattern having narrowed width or a hole disposed under a through-hole for an inner conductor, which electrically connects the strip line pattern and an inner conductor. Dimensions of the high impedance portion are controlled to cancel out parasitic susceptance due to the discontinuous structure. A matching through-hole is further disposed in the second dielectric substrate in an area separated from the tip portion of the strip line pattern by a distance of around 25% of the typical wave length. The matching through-hole is elongated to a land pattern in a hole disposed in the second ground conductor pattern so as to electrically connect the conductor strip pattern and the land pattern.

Abstract translation: 提高了进入带状线的馈电点的高频区域的反射特性，并且通过本文的方法和装置促进了带状线馈电装置的组装。 带状线包括在第一电介质基板的表面上的带状线图案，该第一电介质基板的表面上设置有设置在其相对表面上的接地导体图案，以及设置在第二电介质基板的表面上的第二接地导体图案。 串联高阻抗部分设置在带状线图案的尖端部分附近的区域。 高阻抗部分包括具有变窄的宽度的带状线图案的一部分或设置在用于内导体的通孔下方的孔，其将带状线图案和内导体电连接。 控制高阻抗部分的尺寸以抵消由于不连续结构引起的寄生电容。 在第二电介质基板中，与带状线图案的前端部分隔开约25％的典型波长的距离的区域，进一步配置匹配的通孔。 匹配的通孔被延伸到设置在第二接地导体图案中的孔中的焊盘图案，以便电连接导体带图案和焊盘图案。

公开(公告)号：US20020050403A1

公开(公告)日：2002-05-02

申请号：US09370990

申请日：1999-08-10

Inventor： AKIO YASUKAWA ,  HIROHISA YAMAMURA ,  TATSUYA SHIGEMURA

IPC: H01L023/053

CPC classification number: H01L23/473 ,  H01L23/13 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0306 ,  H05K3/0061 ,  H05K3/341 ,  H05K2201/09745 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A semiconductor device in which fatigue failure of a solder layer underneath a semiconductor chip mounted on a base can be prevented from occurring due to repetitions of turn-on and -off of power during operation thereof, is provided, that is, a recess is formed in the base in a part underneath the semiconductor chip so as to prevent occurrence of thermal expansion in the base.

Abstract translation: 提供了一种半导体装置，其中可以防止在其操作期间由于重复打开和关闭电源而发生安装在基座上的半导体芯片下方的焊料层的疲劳失效，即形成凹部 在半导体芯片下面的部分的基部中，以防止在基底中发生热膨胀。

公开(公告)号：US20020007961A1

公开(公告)日：2002-01-24

申请号：US09866813

申请日：2001-05-30

Inventor： Takeshi Yamato ,  Kenichiro Ito

IPC: H05K001/11 ,  H05K001/03

CPC classification number: G11B5/486 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/06 ,  H05K3/108 ,  H05K3/388 ,  H05K3/4092 ,  H05K3/44 ,  H05K2201/0969 ,  H05K2201/09745 ,  H05K2203/0323

Abstract: To provide a wired circuit board capable of surely preventing occurrence of a short circuit between a metal terminal layer and a metal supporting layer with a simple construction, to provide improvement in connection reliability and in voltage proof property, a wired circuit board comprises a base layer formed on a supporting board, a conductive layer formed on the base layer, a surface of the conductive layer being exposed by opening the supporting board and the base layer, and a metal plated layer formed on the conductive layer exposed in the openings of the supporting board and the base layer, wherein a specified space is defined between a periphery of the metal plated layer and a periphery of the opening of the supporting board.

Abstract translation: 为了提供能够以简单的结构可靠地防止金属端子层和金属支撑层之间发生短路的布线电路板，为了提供连接可靠性和耐电压性能的提高，布线电路板包括基底层 形成在支撑板上的导电层，形成在基底层上的导电层，通过打开支撑板和基底层露出导电层的表面，以及形成在暴露在支撑体的开口中的导电层上的金属镀层 板和基底层，其中在金属镀层的周边和支撑板的开口的周边之间限定了特定的空间。