公开(公告)号：US6158644A

公开(公告)日：2000-12-12

申请号：US70163

申请日：1998-04-30

Applicant: Peter J. Brofman ,  Mark G. Courtney ,  Shaji Farooq ,  Mario J. Interrante ,  Raymond A. Jackson ,  Gregory B. Martin ,  Sudipta K. Ray ,  William E. Sablinski ,  Kathleen A. Stalter

Inventor： Peter J. Brofman ,  Mark G. Courtney ,  Shaji Farooq ,  Mario J. Interrante ,  Raymond A. Jackson ,  Gregory B. Martin ,  Sudipta K. Ray ,  William E. Sablinski ,  Kathleen A. Stalter

IPC: H01L23/12 ,  B23K35/02 ,  B23K35/14 ,  H01L21/60 ,  H01L23/498 ,  H05K3/34 ,  B23K35/24 ,  B23K35/26

CPC classification number: H01L24/12 ,  B23K35/0222 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H05K3/3436 ,  B23K35/0244 ,  H01L2224/1184 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K2203/0435 ,  Y02P70/613 ,  Y10T428/12687 ,  Y10T428/2991

Abstract: This invention relates to a solder structure which provides enhanced fatigue life properties when used to bond substrates particularly at the second level such as BGA and CGA interconnections. The solder structure is preferably a sphere or column and has a metal layer wettable by solder and the structure is used to make solder connections in electronic components such as joining an electronic module such as a chip connected to a MLC which module is connected to a circuit board. The solder structure preferably has an overcoat of solder on the metal layer to provide a passivation coating to the metal layer to keep it clean from oxidation and corrosion and also provide a wettable surface for attachment of the solder structure to solder on the pads of the substrate being bonded.

Abstract translation: 本发明涉及一种焊料结构，当用于特别是在第二层（例如BGA和CGA互连）的基材上时，其提供增强的疲劳寿命特性。 焊料结构优选是球形或柱状，并且具有可被焊料润湿的金属层，并且该结构用于在电子部件中形成焊接连接​​，例如连接诸如连接到MLC的芯片的电子模块，该模块连接到电路 板。 焊料结构优选地在金属层上具有焊料的外涂层，以向金属层提供钝化涂层以保持其免于氧化和腐蚀，并且还提供用于将焊料结构附着到衬底的焊盘上的焊料的可润湿表面 被绑定。

公开(公告)号：US6037193A

公开(公告)日：2000-03-14

申请号：US792073

申请日：1997-01-31

Applicant: Mario J. Interrante ,  Laertis Economikos ,  Lester Wynn Herron

Inventor： Mario J. Interrante ,  Laertis Economikos ,  Lester Wynn Herron

IPC: H01L23/02 ,  H01L23/10 ,  H01L23/28

CPC classification number: H01L23/10 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/163

Abstract: The present invention relates generally to a new process for hermetically sealing of a high thermally conductive substrate, such as, an aluminum nitride substrate, using a low thermally conductive interposer and structure thereof. More particularly, the invention encompasses a hermetic cap which is secured to an aluminum nitride substrate using the novel thermal interposer. The novel thermal interposer basically comprises of layers of relatively high thermal conductive metallic materials sandwiching a core layer of low thermal conductive metallic material.

Abstract translation: 本发明一般涉及一种使用低导热插入件及其结构对诸如氮化铝衬底的高导热衬底进行气密密封的新方法。 更具体地，本发明包括使用新型热插入件固定到氮化铝衬底的密封帽。 新型热插入件基本上由具有较高导热金属材料的层组成，夹层有低导热金属材料的芯层。

公开(公告)号：US5990418A

公开(公告)日：1999-11-23

申请号：US902556

申请日：1997-07-29

Applicant: Kevin G. Bivona ,  Jeffrey T. Coffin ,  Stephen S. Drofitz, Jr. ,  Lewis S. Goldmann ,  Mario J. Interrante ,  Sushumna Iruvanti ,  Raed A. Sherif

Inventor： Kevin G. Bivona ,  Jeffrey T. Coffin ,  Stephen S. Drofitz, Jr. ,  Lewis S. Goldmann ,  Mario J. Interrante ,  Sushumna Iruvanti ,  Raed A. Sherif

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/42 ,  H01L23/02

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/42 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251

Abstract: A device and method for hermetically sealing an integrated circuit chip between a substrate and a lid while providing effective dissipation of heat generated by the integrated circuit chip. The device includes an integrated circuit chip, carrier substrate, interface coolant, and a lid. The integrated circuit chip is attached to the top of the carrier substrate. The interface coolant is disposed on the top of the integrated circuit chip and the lid is placed on top of the carrier substrate/integrated circuit chip combination and contacts the interface coolant. The interface coolant provides a thermal path for conducting heat from the integrated circuit chip to the lid. The substrate is attached to a circuit board by a ceramic ball grid array (CBGA) or a ceramic column grid array (CCGA).

Abstract translation: 一种用于在集成电路芯片产生的热量的有效耗散的同时在衬底和盖子之间气密密封集成电路芯片的装置和方法。 该装置包括集成电路芯片，载体基板，界面冷却剂和盖子。 集成电路芯片附着到载体衬底的顶部。 接口冷却剂设置在集成电路芯片的顶部，并且盖子被放置在载体基板/集成电路芯片组合的顶部上并且接触界面冷却剂。 界面冷却剂提供用于将热量从集成电路芯片传导到盖子的热路径。 衬底通过陶瓷球栅阵列（CBGA）或陶瓷柱栅阵列（CCGA）连接到电路板。

公开(公告)号：US5543584A

公开(公告)日：1996-08-06

申请号：US843684

申请日：1992-02-28

Applicant: Edward F. Handford ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  Raymond A. Jackson ,  Raj N. Master ,  Sudipta K. Ray ,  William E. Sablinski ,  Thomas A. Wassick

Inventor： Edward F. Handford ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  Raymond A. Jackson ,  Raj N. Master ,  Sudipta K. Ray ,  William E. Sablinski ,  Thomas A. Wassick

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/498 ,  H01L23/52 ,  H01L23/525 ,  H01L23/538 ,  H05K3/00 ,  H05K3/02 ,  H05K3/22 ,  H05K3/34 ,  H05K1/11

CPC classification number: H01L21/76892 ,  H01L23/49866 ,  H01L23/525 ,  H05K3/225 ,  H01L2924/0002 ,  H05K2201/10181 ,  H05K2201/10234 ,  H05K2201/1028 ,  H05K2201/10287 ,  H05K2203/0769 ,  H05K2203/107 ,  H05K2203/121 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/0017 ,  H05K3/027 ,  H05K3/34 ,  Y10T29/49124

Abstract: The present invention relates generally to a new method of repairing electrical lines, and more particularly to repairing electrical lines having an opening at the module level with devices in place. Various methods and processes are used to repair this open or defective portion in an electrical conductor line. It could be repaired by securing a jumper wire or nugget across the open or the repair could be made by a deposition process, which includes but is not limited to filling the opening with a solder type material or inserting a solder coated electrical wire and heating the solder and allowing the solder to melt and repair the open. One of the attributes of this invention is the ability to repair on a substrate or module on which active components such as chips, and passive components such as pins, capacitors, etc. have been attached. The invention also allows repair of fine line patterns which are normally not repairable by conventional techniques.

Abstract translation: 本发明一般涉及一种修复电线的新方法，更具体地说，涉及在装置的适当位置修复具有模块级开口的电线。 使用各种方法和过程来修复电导体线中的这个开路或有缺陷的部分。 它可以通过将跨接线或熔核固定在整个开口处进行修复，或者可以通过沉积工艺进行修复，该沉积工艺包括但不限于用焊料型材料填充开口或插入焊料涂覆的电线并加热 焊接并允许焊料熔化并修复开路。 本发明的一个特征是在其上附着有诸如引脚，电容器等的诸如芯片和无源部件的有源部件的基板或模块上进行修复的能力。 本发明还允许修复通常不能通过常规技术修复的细线图案。

公开(公告)号：US08487447B2

公开(公告)日：2013-07-16

申请号：US13111283

申请日：2011-05-19

Applicant: Mario J. Interrante ,  Gary LaFontant ,  Michael J. Shapiro ,  Thomas A. Wassick ,  Bucknell C. Webb

Inventor： Mario J. Interrante ,  Gary LaFontant ,  Michael J. Shapiro ,  Thomas A. Wassick ,  Bucknell C. Webb

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/06131 ,  H01L2224/06134 ,  H01L2224/13005 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2224/05552

Abstract: A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.

Abstract translation: 一种半导体结构，其包括三维结构中的多个层叠半导体芯片。 存在与第二半导体芯片接触的第一半导体芯片。 第一半导体芯片包括延伸穿过第一半导体芯片的贯穿硅通孔（TSV）; 在所述第一半导体芯片的表面处的导电焊盘，所述TSV终止于所述导电焊盘的第一侧接触; 覆盖所述导电焊盘的钝化层，所述钝化层具有多个开口; 以及形成在所述多个开口中并与所述导电垫的第二侧接触的多个导电结构，所述多个导电结构与所述导电垫的接触相对于所述TSV的接触而偏移 与导电垫。

公开(公告)号：US08383505B2

公开(公告)日：2013-02-26

申请号：US13080105

申请日：2011-04-05

Applicant: Luc Guerin ,  Mario J. Interrante ,  Michael J. Shapiro ,  Thuy Tran-Quinn ,  Van T. Truong

Inventor： Luc Guerin ,  Mario J. Interrante ,  Michael J. Shapiro ,  Thuy Tran-Quinn ,  Van T. Truong

IPC: H01L21/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05681 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/05552

Abstract: A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Abstract translation: 焊球接触和制造焊球接触的方法包括：在集成电路（IC）芯片和金属焊盘上形成有通孔的第一绝缘层; 设置在所述通孔内和所述第一绝缘层的围绕所述通孔的部分上的凸块下冶金（UBM）结构; 第二绝缘层，形成在所述UBM结构的位于所述通孔的中心的外部的上表面上; 以及填充通孔并且设置在UBM结构的与通孔接触的内部的上表面上方的焊球，其中在焊球下面的UBM结构具有比焊球更大的直径。

公开(公告)号：US20120292779A1

公开(公告)日：2012-11-22

申请号：US13111283

申请日：2011-05-19

Applicant: MARIO J. INTERRANTE ,  Gary LaFontant ,  Michael J. Shapiro ,  Thomas A. Wassick ,  Bucknell C. Webb

Inventor： MARIO J. INTERRANTE ,  Gary LaFontant ,  Michael J. Shapiro ,  Thomas A. Wassick ,  Bucknell C. Webb

IPC: H01L23/48 ,  H01L21/28

CPC classification number: H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/06131 ,  H01L2224/06134 ,  H01L2224/13005 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2224/05552

Abstract: A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.

Abstract translation: 一种半导体结构，其包括三维结构中的多个层叠半导体芯片。 存在与第二半导体芯片接触的第一半导体芯片。 第一半导体芯片包括延伸穿过第一半导体芯片的贯穿硅通孔（TSV）; 在所述第一半导体芯片的表面处的导电焊盘，所述TSV终止于所述导电焊盘的第一侧接触; 覆盖所述导电焊盘的钝化层，所述钝化层具有多个开口; 以及形成在所述多个开口中并与所述导电垫的第二侧接触的多个导电结构，所述多个导电结构与所述导电垫的接触相对于所述TSV的接触而偏移 与导电垫。

公开(公告)号：US06917113B2

公开(公告)日：2005-07-12

申请号：US10249621

申请日：2003-04-24

Applicant: Mukta G. Farooq ,  Mario J. Interrante

Inventor： Mukta G. Farooq ,  Mario J. Interrante

IPC: H01L23/485 ,  H01L23/498 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L24/10 ,  B23K35/262 ,  B23K2101/36 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10378 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K2203/047 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A lead free solder hierarchy structure for electronic packaging that includes organic interposers. The assembly may also contain passive components as well as underfill material. The lead free solder hierarchy also provides a lead free solder solution for the attachment of a heat sink to the circuit chip with a suitable lead free solder alloy.

Abstract translation: 电子封装的无铅焊料层次结构，包括有机插层。 组件还可以包含无源部件以及底部填充材料。 无铅焊料层次结构还提供无铅焊料溶液，用于使用合适的无铅焊料合金将散热片连接到电路芯片。

公开(公告)号：US06303400B1

公开(公告)日：2001-10-16

申请号：US09404511

申请日：1999-09-23

Applicant: Mario J. Interrante ,  Thomas E. Lombardi ,  Frank L. Pompeo ,  William E. Sablinski

Inventor： Mario J. Interrante ,  Thomas E. Lombardi ,  Frank L. Pompeo ,  William E. Sablinski

IPC: G01R3126

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10992 ,  H05K2203/162 ,  H05K2203/176 ,  Y02P70/613 ,  H01L2924/00

Abstract: A temporary attach article of a first component to a second component which includes a first component having a first volume of a fusible material; a second component having a second volume of fusible material; and the first and second components being joined together through the first and second volumes of fusible material, wherein the first volume of fusible material has a melting point higher than a melting point of the second volume of fusible material so that the first and second components may be joined together without melting of the first volume of fusible material and wherein the second volume of fusible material is 5 to 20% of the first volume of fusible material. Also disclosed is a method for temporary attach of devices to an electronic substrate.

公开(公告)号：US06302732B1

公开(公告)日：2001-10-16

申请号：US09460888

申请日：1999-12-14

Applicant: Mark Budman ,  Mario J. Interrante ,  John U. Knickerbocker

Inventor： Mark Budman ,  Mario J. Interrante ,  John U. Knickerbocker

IPC: H01R905

CPC classification number: H01R9/0515 ,  H01R13/03

Abstract: A coaxial connector having a conductive copper wire core plated with a layer of gold with the layer of gold surrounded by a dielectric layer, such as polyimide. The layer of polyimide is surrounded by a conductive shielding layer, such as copper, with a tin-plated layer surrounding it. Connection of the coaxial connector at one end to adjacent signal and ground pads is achieved by laser ablation to expose a section of gold sufficient to accommodate the terminal pad pitch and allow wire bonding to the signal pad. Connection of the conductive shielding layer to the ground pad is achieved by hot tip soldering. Connection at the opposite end of the coaxial connector uses the same process.

Abstract translation: 一种同轴连接器，其具有镀有金层的导电铜线芯，该金属层由诸如聚酰亚胺之类的电介质层围绕的金属层。 聚酰亚胺层被诸如铜的导电屏蔽层包围，其周围具有镀锡层。 通过激光烧蚀来实现一端与相邻信号和接地焊盘的同轴连接器的连接，以暴露足以容纳端子焊盘间距并允许引线键合到信号焊盘的一部分金。 通过热尖端焊接实现导电屏蔽层与接地焊盘的连接。 同轴连接器相对端的连接使用相同的过程。