公开(公告)号：US08264213B2

公开(公告)日：2012-09-11

申请号：US12470424

申请日：2009-05-21

申请人： Chih-Wei Lin ,  Nung-Te Huang ,  Chih-Wan Hsu

发明人： Chih-Wei Lin ,  Nung-Te Huang ,  Chih-Wan Hsu

IPC分类号： G05F1/575 ,  G05F1/618

CPC分类号： H02M3/1584 ,  H02M3/157 ,  H02M2001/0032 ,  H02M2003/1586 ,  Y02B70/16

摘要： A control method of a variable-frequency and multi-phase voltage regulator module is provided. The variable-frequency and multi-phase voltage regulator module is connected to a central processing unit and embedded on a motherboard for providing a central-processing-unit current. The control method includes steps of: detecting an intensity of a central-processing-unit current of the central processing unit; providing a power to the central processing unit via M number of phases based on a first switching frequency if the intensity of the central-processing-unit current is greater than a reference-current value; and providing a power to the central processing unit via N number of phases based on a second switching frequency if the intensity of the central-processing-unit current is less than the reference-current value.

摘要翻译： 提供了一种变频和多相电压调节器模块的控制方法。 可变频率和多相电压调节器模块连接到中央处理单元并嵌入在主板上以提供中央处理单元电流。 该控制方法包括以下步骤：检测中央处理单元的中央处理单元电流的强度; 如果中央处理单元电流的强度大于参考电流值，则基于第一开关频率经由M个相位来向中央处理单元提供电力; 以及如果所述中央处理单元电流的强度小于所述基准电流值，则基于第二开关频率经由N个相位来向所述中央处理单元提供电力。

公开(公告)号：US08214664B2

公开(公告)日：2012-07-03

申请号：US12483941

申请日：2009-06-12

申请人： Chih-Wei Lin ,  Chih-Wan Hsu ,  Nung-Te Huang

发明人： Chih-Wei Lin ,  Chih-Wan Hsu ,  Nung-Te Huang

IPC分类号： G06F1/26

CPC分类号： G06F1/263

摘要： A power supplying control method of a computer system for use with a first power supply and a second power supply both providing a first specific voltage to a motherboard, including steps of: detecting whether the first power supply and the second power supply, outputting the first specific voltage, are at a stable state; outputting the first specific voltage to a first pin when the first power supply is at the stable state; outputting the first specific voltage to the first pin when the second power supply is at the stable state; and outputting the first specific voltage to the motherboard via the first pin.

摘要翻译： 一种与向主板提供第一特定电压的第一电源和第二电源一起使用的计算机系统的供电控制方法，包括以下步骤：检测第一电源和第二电源，输出第一电源 具体电压处于稳定状态; 当第一电源处于稳定状态时，将第一特定电压输出到第一引脚; 当第二电源处于稳定状态时，将第一特定电压输出到第一引脚; 以及经由所述第一引脚将所述第一特定电压输出到所述母板。

公开(公告)号：US20080197260A1

公开(公告)日：2008-08-21

申请号：US11676294

申请日：2007-02-18

申请人： I-Ching Chou ,  Chih-Wei Lin ,  Yuh-Wen Huang

发明人： I-Ching Chou ,  Chih-Wei Lin ,  Yuh-Wen Huang

IPC分类号： A47B96/00

CPC分类号： G11B33/128 ,  G06F1/187

摘要： A computer housing includes: a housing body; a first supporting plate mounted in the housing body; a second supporting plate mounted in the housing body and cooperating with the first supporting plate to define a mounting space therebetween; and an operating lever pivoted to the second supporting plate, formed with an engaging tongue, and rotatable relative to the second supporting plate between a first angular position, in which the engaging tongue extends into the mounting space for retaining a box-like device in the mounting space, and a second angular position, in which the engaging tongue is disposed outside of the mounting space for permitting removal of the box-like device.

摘要翻译： 计算机壳体包括：壳体; 安装在所述壳体内的第一支撑板; 第二支撑板，其安装在所述壳体中并与所述第一支撑板协作以在其间限定安装空间; 以及操作杆，其枢转到第二支撑板，形成有接合舌片，并且可相对于第二支撑板在第一角位置之间旋转，第一角位置中，接合舌片延伸到安装空间中，以将盒状装置保持在 安装空间和第二角位置，其中接合舌片设置在安装空间的外部，以允许移除盒状装置。

公开(公告)号：US20080150130A1

公开(公告)日：2008-06-26

申请号：US11613247

申请日：2006-12-20

申请人： Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

发明人： Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

IPC分类号： H01L23/48

CPC分类号： H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

摘要： The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the mechanical reliability of the structure during temperature cycling test. The CTE difference between the RDL and the elastic dielectric material still may cause the elastic dielectric layer crack; to solve this problem, The present invention further provides a structure of dielectric layers with certain open through holes adjacent to the curve portion of a RDL of WLP which can reduce the stress accumulated at area of the dielectric layer adjacent to the RDL/dielectric layer interface to solve the crack problem of the dielectric layer.

摘要翻译： 本发明提供了具有与WLP的RDL的角度相邻的某些通孔以吸收应力的弹性介电层的结构。 弹性介电层由具有特定范围的CTE，伸长率和硬度的硅酮基材料制成，这可以在温度循环测试期间提高结构的机械可靠性。 RDL和弹性介电材料之间的CTE差异仍然可能导致弹性介电层裂纹; 为了解决这个问题，本发明还提供了具有与WLP的RDL的曲线部分相邻的某些开放通孔的电介质层的结构，其可以减少在与RDL /介电层界面相邻的介电层的面积处积累的应力 以解决电介质层的裂纹问题。

公开(公告)号：US20080142946A1

公开(公告)日：2008-06-19

申请号：US11609970

申请日：2006-12-13

申请人： Wen-Kun Yang ,  Tung-Chuan Wang ,  Chao-Nan Chou ,  Chih-Wei Lin

发明人： Wen-Kun Yang ,  Tung-Chuan Wang ,  Chao-Nan Chou ,  Chih-Wei Lin

IPC分类号： H01L23/48 ,  H01L21/56

CPC分类号： H01L23/3128 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00

摘要： The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the redistribution built up layer. Terminal Conductive bumps are coupled to the UBM.

摘要翻译： 本发明提供了一种包装结构，其包括具有预先形成的模具容纳空腔的基板和/或形成在基板的上表面内的端接触金属焊盘。 通过粘合将模具设置在模具接收腔内，并且在模具和基板上形成介电层。 在电介质层上形成至少一个重新分配建立层（RDL），并通过接触焊盘与芯片耦合。 连接结构，例如，UBM形成在再分配建立层上。 端子导电凸块耦合到UBM。

公开(公告)号：US07224061B2

公开(公告)日：2007-05-29

申请号：US10918416

申请日：2004-08-16

申请人： Wen-Kun Yang ,  Shih-Li Chen ,  Wen-Bin Sun ,  Ming-Hui Lin ,  Chao-Nan Chou ,  Chih-Wei Lin

发明人： Wen-Kun Yang ,  Shih-Li Chen ,  Wen-Bin Sun ,  Ming-Hui Lin ,  Chao-Nan Chou ,  Chih-Wei Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3114 ,  H01L23/3128 ,  H01L24/19 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2924/01029 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

摘要： A package structure including a device, an interconnecting element, a pad and a protecting element is provided. The device connects with a first end of the interconnecting element through the pad. The protecting element covers the pad and the first end of the interconnecting element.

摘要翻译： 提供包括器件，互连元件，焊盘和保护元件的封装结构。 该装置通过焊盘与互连元件的第一端连接。 保护元件覆盖焊盘和互连元件的第一端。

公开(公告)号：US09768137B2

公开(公告)日：2017-09-19

申请号：US13460412

申请日：2012-04-30

申请人： Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chih-Wei Lin ,  Cheng-Ting Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

发明人： Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chih-Wei Lin ,  Cheng-Ting Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L23/367

CPC分类号： H01L24/14 ,  H01L21/4853 ,  H01L23/3677 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/1134 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.

公开(公告)号：US09607921B2

公开(公告)日：2017-03-28

申请号：US13349405

申请日：2012-01-12

申请人： Wen-Hsiung Lu ,  Yi-Wen Wu ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

发明人： Wen-Hsiung Lu ,  Yi-Wen Wu ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/3192 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/03823 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05548 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/10126 ,  H01L2224/11464 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/73104 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

摘要： A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer.

公开(公告)号：US09598772B2

公开(公告)日：2017-03-21

申请号：US12761863

申请日：2010-04-16

申请人： Chih-Wei Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chung-Shi Liu

发明人： Chih-Wei Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chung-Shi Liu

IPC分类号： H01L23/498 ,  H01L21/3205 ,  C23C18/16 ,  H01L23/00 ,  H01L23/31

CPC分类号： C23C18/1605 ,  C23C18/165 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2924/0002 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method for fabricating bump structure without UBM undercut uses an electroless Cu plating process to selectively form a Cu UBM layer on a Ti UBM layer within an opening of a photoresist layer. After stripping the photoresist layer, there is no need to perform a wet etching process on the Cu UBM layer, and thereby the UBM structure has a non-undercut profile.

公开(公告)号：US08975741B2

公开(公告)日：2015-03-10

申请号：US13275065

申请日：2011-10-17

申请人： Chih-Wei Lin ,  Ming-Da Cheng ,  Meng-Tse Chen ,  Wen-Hsiung Lu ,  Kuei-Wei Huang ,  Chung-Shi Liu

发明人： Chih-Wei Lin ,  Ming-Da Cheng ,  Meng-Tse Chen ,  Wen-Hsiung Lu ,  Kuei-Wei Huang ,  Chung-Shi Liu

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L25/50 ,  H01L21/31051 ,  H01L21/31127 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76885 ,  H01L21/786 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/27019 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/82005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1047 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00

摘要： A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.

摘要翻译： 器件包括层间电介质，在层间电介质下的器件管芯; 以及在所述层间电介质和所述器件管芯之下的管芯附着膜，其中所述管芯附着膜附接到所述器件管芯。 多个再分配线包括与芯片附着膜水平的部分。 多个Z互连电子耦合到器件裸片和多个再分配线。 含聚合物的材料在层间电介质的下方。 器件管芯，管芯附着膜和多个Z形互连件设置在包含聚合物的材料中。