公开(公告)号：US09404193B1

公开(公告)日：2016-08-02

申请号：US15079533

申请日：2016-03-24

Applicant: Rohm and Haas Electronic Materials LLC

Inventor： Julia Kozhukh ,  Zuhra I. Niazimbetova ,  Maria Anna Rzeznik

IPC: C25D3/32 ,  C25D3/38 ,  C25D3/02 ,  C25D3/56 ,  C25D5/54 ,  C25D5/56 ,  H05K3/18 ,  H05K3/42 ,  C25D5/02

CPC classification number: C25D3/38 ,  C07C279/08 ,  C07C279/18 ,  C07C311/64 ,  C07C335/24 ,  C07D303/10 ,  C25D3/02 ,  C25D3/32 ,  C25D3/56 ,  C25D3/565 ,  C25D3/60 ,  C25D5/02 ,  C25D5/54 ,  C25D5/56 ,  C25D7/123 ,  H05K3/188 ,  H05K3/424 ,  H05K2201/09509 ,  H05K2201/09563

Abstract: Reaction products of guanidine compounds or salts thereof, polyepoxide compounds and polyhalogen compounds may be used as levelers in metal electroplating baths, such as copper electroplating baths, to provide good throwing power. Such reaction products may plate with good surface properties of the metal deposits and good physical reliability.

公开(公告)号：US09324474B2

公开(公告)日：2016-04-26

申请号：US14554971

申请日：2014-11-26

Applicant: Robert Bosch GmbH

Inventor： Heribert Weber ,  Yvonne Bergmann ,  Klaus Krueger ,  Andreas Rathjen

IPC: H01B1/22 ,  C09D11/322 ,  H05K1/09 ,  H05K3/40 ,  C09D11/52 ,  H01L21/283 ,  H05K3/12

CPC classification number: H01B1/22 ,  C09D11/322 ,  C09D11/52 ,  H01L21/283 ,  H01L21/288 ,  H01L21/76898 ,  H01L2224/24145 ,  H01L2224/48091 ,  H01L2924/00014 ,  H05K1/097 ,  H05K3/1241 ,  H05K3/125 ,  H05K3/403 ,  H05K3/4053 ,  H05K2201/0266 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2203/1105 ,  H01L2224/45099

Abstract: A dispersion is provided having a dispersion medium and a plurality of colloid particles finely distributed in the dispersion medium, the colloid particles being electrically conductive, the dispersion being a functional ink for the wetting of an inner wall of a contacting opening of a substrate using a print process.

Abstract translation: 提供了具有分散介质和细分散在分散介质中的多个胶体颗粒的分散体，胶体颗粒是导电的，该分散体是用于润湿基材的接触开口的内壁的功能油墨，其使用 打印过程。

公开(公告)号：US09320153B2

公开(公告)日：2016-04-19

申请号：US14548725

申请日：2014-11-20

Applicant: IBIDEN CO., LTD.

Inventor： Masahiro Kaneko ,  Satoru Kose ,  Hirokazu Higashi

IPC: H05K3/02 ,  H05K3/10 ,  H05K3/42 ,  H01L21/683 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H05K1/11 ,  H05K1/03 ,  H05K3/22 ,  H05K3/00 ,  H05K3/38

CPC classification number: H05K3/42 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0313 ,  H05K1/113 ,  H05K1/115 ,  H05K3/007 ,  H05K3/108 ,  H05K3/22 ,  H05K3/388 ,  H05K2201/0344 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/1377 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed wiring board includes an interlayer resin insulation layer having a penetrating hole, a conductive circuit formed on a first surface of the interlayer resin insulation layer, a filled via conductor formed in the penetrating hole of the interlayer resin insulation layer and connected to the conductive circuit, a first surface-treatment coating structure formed on a first surface of the filled via conductor and having an electroless plating structure, and a second surface-treatment coating structure formed on a second surface of the filled via conductor on an opposite side with respect to the first surface-treatment coating structure and having an electroless plating structure. The filled via conductor includes a first conductive layer formed on side wall of the penetrating hole and a plated material filling the penetrating hole, and the first surface-treatment coating structure has a thickness which is different from a thickness of the second surface-treatment coating structure.

Abstract translation: 印刷电路板包括具有贯通孔的层间树脂绝缘层，形成在层间树脂绝缘层的第一表面上的导电电路，形成在层间树脂绝缘层的穿透孔中并与导电 电路，形成在填充的通路导体的第一表面上并具有无电解电镀结构的第一表面处理涂层结构和形成在填充通孔导体的第二表面上的第二表面处理涂层结构，该第二表面处理涂层结构相对于 涉及第一表面处理涂层结构并具有化学镀层结构。 填充的通孔导体包括形成在穿透孔的侧壁上的第一导电层和填充穿透孔的电镀材料，第一表面处理涂层结构的厚度与第二表面处理涂层的厚度不同 结构体。

公开(公告)号：US09295150B2

公开(公告)日：2016-03-22

申请号：US14035957

申请日：2013-09-25

Applicant: Zhen Ding Technology Co., Ltd.

Inventor： Wen-Hung Hu

IPC: H05K1/02 ,  H05K3/46 ,  H05K3/42 ,  H05K1/11

CPC classification number: H05K1/0298 ,  H05K1/115 ,  H05K3/421 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49165

Abstract: A printed circuit board includes a first, second, and third dielectric layers, and a first, second, and third trace layers. The first trace layer and the second trace layer are formed on opposite surfaces of the first dielectric layer. The second dielectric layer is formed on the second trace layer, a first blind hole is defined in the first surface and terminated at a position in the first dielectric layer, a first conductive via is formed in the first blind hole. A second blind hole is formed in the second dielectric layer and the first dielectric layer. A second conductive via is formed in the second blind hole. The third trace layer is electrically connected with the second conductive via. The first trace layer is electrically connected with the second trace layer through the first conductive via and the second conductive via.

Abstract translation: 印刷电路板包括第一，第二和第三电介质层，以及第一，第二和第三迹线层。 第一迹线层和第二迹线层形成在第一介电层的相对表面上。 第二电介质层形成在第二迹线层上，第一盲孔被限定在第一表面中并且终止于第一电介质层中的位置，第一导电通孔形成在第一盲孔中。 在第二电介质层和第一电介质层中形成第二盲孔。 第二导电通孔形成在第二盲孔中。 第三迹线层与第二导电通孔电连接。 第一迹线层通过第一导电通孔和第二导电通孔与第二迹线层电连接。

公开(公告)号：US20160057857A1

公开(公告)日：2016-02-25

申请号：US14817378

申请日：2015-08-04

Applicant: International Business Machines Corporation

Inventor： Hiroyuki Mori ,  Hirokazu Noma ,  Keishi Okamoto

IPC: H05K1/03 ,  H05K1/11 ,  G03F7/32 ,  G03F7/40 ,  G03F7/16 ,  G03F7/20

CPC classification number: G03F7/0035 ,  G03F7/38 ,  H05K3/428 ,  H05K3/4679 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09845 ,  H05K2203/0577 ,  H05K2203/0588 ,  H05K2203/1453

Abstract: A method of forming a circuit board includes forming a conductive pattern on a substrate; forming a first negative resist on the substrate after formation of the conductive pattern; partially exposing the first negative resist on the surface of the conductive pattern to form a first via exposure portion; forming a second negative resist on the substrate after formation of the first via exposure portion; partially exposing the second negative resist on the first via exposure portion to form a second via exposure portion larger than the first via exposure portion; developing the first negative resist and the second negative resist after formation of the second via exposure portion to form a via opening reaching the conductive pattern; and filling the via opening with a conductive material.

Abstract translation: 一种形成电路板的方法包括在基板上形成导电图案; 在形成导电图案之后在衬底上形成第一负抗蚀剂; 在导电图案的表面部分地暴露第一负抗蚀剂以形成第一通孔曝光部分; 在形成第一通孔曝光部分之后在基板上形成第二负光刻胶; 在所述第一通孔曝光部分上部分曝光所述第二负光刻胶，以形成大于所述第一通孔曝光部分的第二通孔曝光部分; 在形成第二通孔曝光部分之后显影第一负光刻胶和第二负光刻胶，以形成到达导电图案的通孔; 并用导电材料填充通孔。

公开(公告)号：US09226399B2

公开(公告)日：2015-12-29

申请号：US12952234

申请日：2010-11-23

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H01G4/00 ,  H05K1/16 ,  H05K1/18 ,  H01L23/498 ,  H01L23/50 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/417 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A wiring board with built-in capacitors includes a core substrate, and a high dielectric sheet including a lower electrode layer, an upper electrode layer and a dielectric layer, the dielectric layer made of a sintered ceramic body and sandwiched between the lower electrode layer and the upper electrode layer, the lower electrode layer and/or the upper electrode layer being partitioned into multiple electrodes such that the high dielectric sheet has multiple capacitors. The lower electrode layer and/or the upper electrode layer is connected to a ground line and the other one of the lower electrode layer and the upper electrode layer is connected to a power line such that the capacitors are electrically connected in parallel.

Abstract translation: 具有内置电容器的布线板包括芯基板和包括下电极层，上电极层和电介质层的高电介质层，所述电介质层由烧结陶瓷体制成并夹在下电极层和 上电极层，下电极层和/或上电极层分隔成多个电极，使得高电介质片具有多个电容器。 下电极层和/或上电极层连接到接地线，并且下电极层和上电极层中的另一个连接到电源线，使得电容器并联电连接。

公开(公告)号：US20150348878A1

公开(公告)日：2015-12-03

申请号：US14821818

申请日：2015-08-10

Applicant: Petteri Palm ,  Risto Tuominen ,  Antti Iihola

Inventor： Petteri Palm ,  Risto Tuominen ,  Antti Iihola

IPC: H01L23/498

CPC classification number: H05K1/09 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/351 ,  H05K1/182 ,  H05K1/188 ,  H05K3/305 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/0969 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Manufacturing method and circuit module, which comprises an insulator layer and, inside the insulator layer, at least one component, which comprises contact areas, the material of which contains a first metal. On the surface of the insulator layer are conductors, which comprise at least a first layer and a second layer, in such a way that at least the second layer contains a second metal. The circuit module comprises contact elements between the contact areas and the conductors for forming electrical contacts. The contact elements, for their part, comprise, on the surface of the material of the contact area, an intermediate layer, which contains a third metal, in such a way that the first, second, and third metals are different metals and the contact surface area (ACONT 1), between the intermediate layer and the contact area is less that the surface area (APAD) of the contact area.

公开(公告)号：US09153541B2

公开(公告)日：2015-10-06

申请号：US12032444

申请日：2008-02-15

Applicant: Junji Tanaka

Inventor： Junji Tanaka

IPC: H01L23/02 ,  H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/12 ,  H01L23/053 ,  H01L29/40 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/18 ,  H01L25/03 ,  H05K1/11 ,  H05K3/20 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/113 ,  H05K1/187 ,  H05K3/20 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2203/049 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a first insulator film having a first opening, a first wiring layer extending from the first opening onto the first insulator film, a first semiconductor chip mounted on the first insulator film so as to be electrically coupled with the first wiring layer, and a resin portion applied on the first insulation film to cover the first semiconductor chip.

Abstract translation: 半导体器件包括具有第一开口的第一绝缘膜，从第一开口延伸到第一绝缘膜上的第一布线层，安装在第一绝缘膜上以与第一布线层电耦合的第一半导体芯片， 以及施加在第一绝缘膜上以覆盖第一半导体芯片的树脂部分。

公开(公告)号：US09107332B2

公开(公告)日：2015-08-11

申请号：US13864232

申请日：2013-04-16

Applicant: Zhen Ding Technology Co., Ltd.

Inventor： Wen-Hung Hu

IPC: H05K1/09 ,  H05K3/34 ,  H05K3/40 ,  H05K3/24 ,  H05K3/42

CPC classification number: H05K3/3452 ,  H05K3/244 ,  H05K3/4007 ,  H05K3/4046 ,  H05K3/428 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/099 ,  H05K2203/0571 ,  H05K2203/0577 ,  H05K2203/1383 ,  Y10T29/49167

Abstract: A printed circuit board includes a base, a circuit pattern, a solder mask, an activated metal layer, a plurality of metal seed layers, and a plurality of metal bumps. The conductive circuit pattern is formed on the base, to include a plurality of conductive pads. The solder mask is formed on a surface of the conductive circuit pattern and portions of the base are exposed from the circuit pattern. The solder mask includes blind vias corresponding to the pads, and laser-activated catalyst. The activated metal layer is obtained by laser irradiation at the wall of the blind via. The activated metal layer is in contact with the solder mask. The metal seed layer is formed on the activated metal layer and the pads. Each metal bump is formed on the metal seed layer, and each metal bump protrudes from the solder mask.

Abstract translation: 印刷电路板包括基底，电路图案，焊接掩模，活化金属层，多个金属种子层和多个金属凸块。 导电电路图案形成在基底上，以包括多个导电焊盘。 焊接掩模形成在导电电路图案的表面上，并且基底的部分从电路图案露出。 焊接掩模包括对应于焊盘的盲孔和激光活化催化剂。 激活的金属层通过激光照射在盲孔的壁处获得。 活化的金属层与焊料掩模接触。 在活化的金属层和焊盘上形成金属种子层。 每个金属凸块形成在金属种子层上，并且每个金属凸块从焊接掩模突出。

公开(公告)号：US20150201499A1

公开(公告)日：2015-07-16

申请号：US14153071

申请日：2014-01-12

Applicant: Zohar SHINAR ,  Joel VIDAL

Inventor： Zohar SHINAR ,  Joel VIDAL

IPC: H05K3/12 ,  B29C67/00

CPC classification number: H05K3/125 ,  B29C64/112 ,  B29C64/135 ,  B29C64/386 ,  B29C70/882 ,  B29K2105/0058 ,  B29K2995/0005 ,  B29K2995/0006 ,  B29K2995/0007 ,  B29L2031/3406 ,  B29L2031/3425 ,  B33Y30/00 ,  B33Y50/02 ,  B33Y80/00 ,  H05K1/0206 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/0274 ,  H05K1/028 ,  H05K1/0281 ,  H05K1/0284 ,  H05K1/092 ,  H05K1/165 ,  H05K1/167 ,  H05K1/186 ,  H05K3/0005 ,  H05K3/1283 ,  H05K3/225 ,  H05K3/284 ,  H05K3/4007 ,  H05K3/4069 ,  H05K3/4664 ,  H05K3/4685 ,  H05K3/4688 ,  H05K2201/0367 ,  H05K2201/037 ,  H05K2201/0391 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/098 ,  H05K2201/09836 ,  H05K2201/09845 ,  H05K2201/09872 ,  H05K2201/10098 ,  H05K2203/013 ,  H05K2203/107 ,  H05K2203/163 ,  H05K2203/166

Abstract: Device, system, and method of three-dimensional printing. A device includes: a first 3D-printing head to selectively discharge conductive 3D-printing material; a second 3D-printing head to selectively discharge insulating 3D-printing material; and a processor to control operations of the first and second 3D-printing heads based on a computer-aided design (CAD) scheme describing a printed circuit board (PCB) intended for 3D-printing. A 3D-printer device utilizes 3D-printing methods, in order to 3D-print: (a) a functional multi-layer PCB; or (b) a functional stand-alone electric component; or (c) a functional PCB having an embedded or integrated electric component, both of them 3D-printed in a unified 3D-printing process.

Abstract translation: 三维打印的设备，系统和方法。 一种装置包括：第一3D打印头，用于选择性地排放导电3D打印材料; 第二3D打印头，用于选择性地放电绝缘3D打印材料; 以及基于描述用于3D打印的印刷电路板（PCB）的计算机辅助设计（CAD）方案来控制第一和第二3D打印头的操作的处理器。 3D打印机设备利用3D打印方法，以便3D打印：（a）功能性多层PCB; 或（b）功能独立电气部件; 或（c）具有嵌入或集成电气部件的功能PCB，它们都以统一的3D打印过程3D打印。