公开(公告)号：US20100105200A1

公开(公告)日：2010-04-29

申请号：US12651758

申请日：2010-01-04

Applicant: Yaojian Lin ,  Xu-Sheng Bao

Inventor： Yaojian Lin ,  Xu-Sheng Bao

IPC: H01L21/60

CPC classification number: H05K3/3452 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13011 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1613 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/112 ,  H05K3/3436 ,  H05K3/3457 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/099 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/014

Abstract: A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed over the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed over the substrate. In one case, the UBM layer is disposed above the passivation layer. Alternatively, the passivation layer is disposed above the UBM layer. A portion of the passivation layer is removed to create a passivation island. The passivation island is centered with respect to the contact pad with its top surface devoid of the UBM layer. A solder bump is formed over the passivation island in electrical contact with the UBM layer. The passivation island forms a void in the solder bump for stress relief. The UBM layer may include a redistribution layer such that the passivation island is offset from the contact pad.

Abstract translation: 倒装片式半导体封装具有在其上形成有多个有源器件的衬底。 接触垫形成在衬底上。 凸块下金属化（UBM）层与接触焊盘电接触。 钝化层形成在衬底上。 在一种情况下，UBM层设置在钝化层上方。 或者，钝化层设置在UBM层上。 去除钝化层的一部分以产生钝化岛。 钝化岛相对于接触焊盘居中，其顶表面不含UBM层。 在与UBM层电接触的钝化岛上形成焊料凸点。 钝化岛在焊料凸块中形成空隙以消除应力。 UBM层可以包括再分布层，使得钝化岛从接触垫偏移。

公开(公告)号：US07705247B2

公开(公告)日：2010-04-27

申请号：US11490312

申请日：2006-07-21

Applicant: Bong-Suck Kim ,  Gye-Soo Kim ,  Jong-Hyung Kim ,  Il-Woon Shin

Inventor： Bong-Suck Kim ,  Gye-Soo Kim ,  Jong-Hyung Kim ,  Il-Woon Shin

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/421 ,  H05K1/115 ,  H05K3/0035 ,  H05K2201/0215 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/025 ,  H05K2203/0554 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A built-up printed circuit board includes stacked micro via-holes, each of which is provided for interconnection between layers in the printed circuit board, and in each of which a filling material, such as liquefied resin or conductive paste, is filled using a poly screen of a general screen printing machine.

Abstract translation: 积层印刷电路板包括堆叠的微通孔，每个微通孔被设置用于印刷电路板中的层之间的互连，并且其中每个通孔使用诸如液化树脂或导电浆料填充材料 一般丝网印刷机的多屏。

公开(公告)号：US07678660B2

公开(公告)日：2010-03-16

申请号：US11252597

申请日：2005-10-19

Applicant: Koichi Tanaka

Inventor： Koichi Tanaka

IPC: H01L21/20

CPC classification number: H05K1/162 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/40 ,  H01L2924/0002 ,  H05K3/0023 ,  H05K3/005 ,  H05K3/107 ,  H05K3/4602 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2203/0108 ,  H05K2203/0551 ,  H05K2203/1189 ,  H01L2924/00

Abstract: A method of manufacturing a capacitor device of the present invention, includes the steps of, forming an insulating layer on a substrate, forming a recess portion in the insulating layer by an imprinting process, forming a lower electrode by filling a metal layer in the recess portion in the insulating layer, forming a photosensitive dielectric layer on the lower electrode, forming an upper electrode on the dielectric layer, and forming a dielectric layer pattern under the upper electrode by exposing/developing the dielectric layer while using the upper electrode as a mask.

公开(公告)号：US20100043942A1

公开(公告)日：2010-02-25

申请号：US12614576

申请日：2009-11-09

Applicant: Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

Inventor： Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

IPC: B32B38/00 ,  B32B38/10

CPC classification number: H05K1/185 ,  H01L24/19 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/188 ,  H05K3/382 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract translation: 通过提供具有第一绝缘层和导电膜的层叠体的方法制造印刷线路板。 通过去除导电膜的至少一部分，在层压体中形成对准标记。 将电子部件放置在基于对准标记确定的位置上设置在第一绝缘层上的粘合剂层上。 在将电子部件封装在第二绝缘层的开口内之后，在基于用于确定电子部件的位置的对准标记确定的位置处形成暴露电子部件的端子的通孔。 通孔导体形成在通孔中，导电层形成在导电膜上并被图案化以形成连接到通孔导体的导电电路。

公开(公告)号：US07667335B2

公开(公告)日：2010-02-23

申请号：US11858749

申请日：2007-09-20

Applicant: Yaojian Lin ,  Xu Sheng Bao

Inventor： Yaojian Lin ,  Xu Sheng Bao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K3/3452 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13011 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1613 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/112 ,  H05K3/3436 ,  H05K3/3457 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/099 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/014

Abstract: A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed over the substrate. In one case, the UBM layer is disposed above the passivation layer. Alternatively, the passivation layer is disposed above the UBM layer. A portion of the passivation layer is removed to create a passivation island. The passivation island is centered with respect to the contact pad with its top surface devoid of the UBM layer. A solder bump is formed over the passivation island in electrical contact with the UBM layer. The passivation island forms a void in the solder bump for stress relief. The UBM layer may include a redistribution layer such that the passivation island is offset from the contact pad.

Abstract translation: 倒装片式半导体封装具有在其上形成有多个有源器件的衬底。 在基板上形成接触垫。 凸块下金属化（UBM）层与接触焊盘电接触。 钝化层形成在衬底上。 在一种情况下，UBM层设置在钝化层上方。 或者，钝化层设置在UBM层上。 去除钝化层的一部分以产生钝化岛。 钝化岛相对于接触焊盘居中，其顶表面没有UBM层。 在与UBM层电接触的钝化岛上形成焊料凸点。 钝化岛在焊料凸块中形成空隙以消除应力。 UBM层可以包括再分布层，使得钝化岛从接触垫偏移。

公开(公告)号：US20100038127A1

公开(公告)日：2010-02-18

申请号：US12605198

申请日：2009-10-23

Applicant: Gary A. Brist ,  Gary Baxter Long ,  Daryl A. Sato

Inventor： Gary A. Brist ,  Gary Baxter Long ,  Daryl A. Sato

IPC: H05K1/11

CPC classification number: H05K1/0265 ,  H05K1/0206 ,  H05K1/0219 ,  H05K1/0221 ,  H05K3/005 ,  H05K3/4644 ,  H05K2201/09036 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09981 ,  H05K2203/0108 ,  H05K2203/1189 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.

Abstract translation: 一种包括多个金属化平面的装置，一个或多个分离多个金属化平面的电介质层; 以及连接到所述多个金属化平面中的至少一个的一个或多个导电沟槽。

公开(公告)号：US07656017B2

公开(公告)日：2010-02-02

申请号：US11953340

申请日：2007-12-10

Applicant: Hyun Joung Kim ,  Taeg Ki Lim ,  Ja Eun Yun

Inventor： Hyun Joung Kim ,  Taeg Ki Lim ,  Ja Eun Yun

IPC: H01L23/02

CPC classification number: H05K3/368 ,  H01L24/45 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10303 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit package system includes providing a plurality of substrates; inserting a receptor in one of the substrates, the receptor held in and not extending through the one of the substrates; inserting a conductive post in another of the substrates; mounting the one of the substrates and the another of the substrates over one another with the conductive post engaging the receptor to thermally interlock without a separate bonding material; and mounting an integrated circuit mounted on the one of the substrates or the another of the substrates.

Abstract translation: 集成电路封装系统包括提供多个基板; 将接收器插入其中一个基板中，所述接收器保持在所述基板中并且不延伸通过所述基板之一; 在另一个基板中插入导电柱; 将一个基板和另一个基板彼此安装，其中导电柱接合接收器以热互锁而没有单独的接合材料; 以及安装安装在一个基板或另一个基板上的集成电路。

公开(公告)号：US20100018634A1

公开(公告)日：2010-01-28

申请号：US12574309

申请日：2009-10-06

Applicant: Michimasa TAKAHASHI ,  Masakazu Aoyama

Inventor： Michimasa TAKAHASHI ,  Masakazu Aoyama

IPC: H05K3/46

CPC classification number: H05K3/4691 ,  H05K1/0218 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4664 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/096 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method of manufacturing a flex-rigid wiring board including disposing a flexible board comprising a flexible substrate and a conductor pattern formed over the flexible substrate and a non-flexible substrate adjacent to each other, covering a boundary between the flexible board and the non-flexible substrate with an insulating layer comprising an inorganic material, providing a conductor pattern on the insulating layer, forming a via hole opening which passes through the insulating layer and reaches the conductor pattern of the flexible board, and plating the via hole opening to form a via connecting the conductor pattern of the flexible board and the conductor pattern on the insulating layer.

Abstract translation: 一种挠性刚性布线板的制造方法，其特征在于，在柔性基板和柔性基板上形成的柔性基板和导体图案之间设置柔性基板，以及相互邻接的非柔性基板， 具有包含无机材料的绝缘层的柔性基板，在绝缘层上提供导体图案，形成穿过绝缘层并到达柔性板的导体图案的通孔开口，以及电镀通孔开口形成 通过连接柔性板的导体图案和绝缘层上的导体图案。

公开(公告)号：US07636231B2

公开(公告)日：2009-12-22

申请号：US12055467

申请日：2008-03-26

Applicant: John S. Guzek ,  Cengiz A. Palanduz ,  Victor Prokofiev

Inventor： John S. Guzek ,  Cengiz A. Palanduz ,  Victor Prokofiev

IPC: H01G4/06

CPC classification number: H01L23/49822 ,  H01G4/236 ,  H01G4/33 ,  H01L21/4857 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/15312 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09718 ,  Y10T29/435 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A thin-film capacitor assembly includes two plates that are accessed through deep and shallow vias. The thin-film capacitor assembly is able to be coupled with a spacer and an interposer. The thin-film capacitor assembly is also able to be stacked with a plurality of thin-film capacitor assemblies. The thin-film capacitor assembly is also part of computing system.

Abstract translation: 薄膜电容器组件包括通过深和浅通孔访问的两个板。 薄膜电容器组件能够与间隔件和插入件耦合。 薄膜电容器组件也能够与多个薄膜电容器组件堆叠。 薄膜电容器组件也是计算系统的一部分。

公开(公告)号：US20090283299A1

公开(公告)日：2009-11-19

申请号：US12427605

申请日：2009-04-21

Applicant: Daigo SUZUKI

Inventor： Daigo SUZUKI

IPC: H05K1/09 ,  H05K3/10

CPC classification number: H05K1/186 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/01046 ,  H01L2924/01078 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/0209 ,  H05K3/0061 ,  H05K3/403 ,  H05K3/4069 ,  H05K3/429 ,  H05K2201/09145 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/10204 ,  Y10T29/49124

Abstract: According to one embodiment, a component-embedded printed circuit board is provided with a built-in component mounted on a component mounting surface of a substrate and enclosed by an insulating layer, an interior pattern layer for heat radiation which is provided on the opposite side of the built-in component from the substrate and radiates heat generated from the built-in component, and an exterior pattern layer for heat radiation connected to the interior pattern layer for heat radiation.

Abstract translation: 根据一个实施例，组件嵌入式印刷电路板设置有安装在基板的部件安装表面上并由绝缘层包围的内置部件，用于散热的内部图案层，其设置在相对侧 并且辐射从内置部件产生的热量，以及用于散热的外部图案层，其连接到用于散热的内部图案层。