公开(公告)号：US20080171172A1

公开(公告)日：2008-07-17

申请号：US12007795

申请日：2008-01-15

Applicant: Won-Cheol Bae ,  Je-Gwang Yoo ,  Sang-Chul Lee ,  Doo-Hwan Lee

Inventor： Won-Cheol Bae ,  Je-Gwang Yoo ,  Sang-Chul Lee ,  Doo-Hwan Lee

IPC: H05K1/11 ,  B32B3/06

CPC classification number: H05K1/185 ,  B32B3/06 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H05K2201/09509 ,  H05K2203/308 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T156/1056 ,  Y10T428/22 ,  H01L2224/82

Abstract: A component-embedded PCB and a method of manufacturing the PCB are disclosed. Using a method that includes perforating a cavity in a core substrate; inserting a component in the cavity; stacking a film layer over the core substrate; forming at least one post by selectively leaving behind the film layer in correspondence to a position of at least one electrode of the component; covering an insulation layer over the core substrate such that the post penetrates the insulation layer to be exposed at a surface of the insulation layer; and forming at least one via hole by removing the post, can provide increased precision and finer pitch. Also, since laser is not used when processing the vias, damage to the component that may occur due to the laser is prevented. Furthermore, tolerance defects may be decreased, as well as defects caused by residue left after processing.

Abstract translation: 公开了一种组件嵌入式PCB及其制造方法。 使用包括在芯基板中穿孔的方法; 将部件插入腔中; 在芯基板上堆叠薄膜层; 通过选择性地将所述膜层留在所述元件的至少一个电极的位置上而形成至少一个柱; 覆盖所述芯基板上的绝缘层，使得所述柱穿透所述绝缘层以在所述绝缘层的表面上暴露; 并且通过去除柱形成至少一个通孔，可以提供更高的精度和更细的间距。 此外，由于在加工通孔时不使用激光，因此防止了由于激光而可能发生的部件的损坏。 此外，可能会降低公差缺陷，以及加工后残留物造成的缺陷。

公开(公告)号：US07387917B2

公开(公告)日：2008-06-17

申请号：US11086625

申请日：2005-03-22

Applicant: Jae Min Choi ,  Young Hwan Shin

Inventor： Jae Min Choi ,  Young Hwan Shin

IPC: H01L21/00

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/19043 ,  H05K1/113 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10378 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed is a ball grid array (BGA) package substrate, in which a wire bonding pad and a solder ball pad are formed on a via hole, making high freedom in design of a circuit pattern and a high density circuit pattern possible, and a method of fabricating the same.

Abstract translation: 公开了一种球栅阵列（BGA）封装基板，其中引线接合焊盘和焊球焊盘形成在通孔上，使电路图案的设计和高密度电路图案具有高自由度，以及方法 的制造。

公开(公告)号：US20080130196A1

公开(公告)日：2008-06-05

申请号：US11744250

申请日：2007-05-04

Applicant: Akihiro Kanno ,  Naohiko Abe ,  Akiko Sugioka ,  Yasuaki Mashiko

Inventor： Akihiro Kanno ,  Naohiko Abe ,  Akiko Sugioka ,  Yasuaki Mashiko

IPC: H01G4/008 ,  B32B15/04

CPC classification number: H01G4/228 ,  H01G4/008 ,  H01G4/12 ,  H05K1/09 ,  H05K1/162 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  Y10T428/26 ,  Y10T428/31678

Abstract: It is an object of the present invention to provide a capacitor layer forming material which is applicable to printed wiring boards manufactured through a high-temperature processing of 300° C. to 400° C. of a fluorine-contained resin substrate, a liquid crystal polymer and the like, and exhibits no deterioration of the strength after a high-temperature heating. In order to achieve the object, a capacitor layer forming material for a printed wiring board which comprises a first conductive layer used for forming a top electrode, a second conductive layer used for forming a bottom electrode and a dielectric layer between the first and second conductive layers, characterized in that for the second conductive layer, a nickel layer or a nickel alloy layer is employed. The nickel layer or the nickel alloy layer as the second conductive layer preferably has a thickness of 10 micron meter to 100 micron meter. Further, the sol-gel method is suitably employed to form the dielectric layer on the nickel layer or the nickel alloy layer constituting the second conductive layer.

Abstract translation: 本发明的目的是提供一种电容器层形成材料，其适用于通过含氟树脂基板的300℃至400℃的高温加工制造的印刷线路板，液晶 聚合物等，并且在高温加热后表现出强度的劣化。 为了实现该目的，用于印刷电路板的电容器层形成材料包括用于形成顶部电极的第一导电层，用于形成底部电极的第二导电层和介于第一和第二导电层之间的介电层 层，其特征在于，对于第二导电层，采用镍层或镍合金层。 作为第二导电层的镍层或镍合金层优选具有10微米至100微米的厚度。 此外，溶胶 - 凝胶法适合用于在构成第二导电层的镍层或镍合金层上形成电介质层。

公开(公告)号：US20080123302A1

公开(公告)日：2008-05-29

申请号：US11734386

申请日：2007-04-12

Applicant: Hiroshi KAWANO ,  Munenori FUJIMURA ,  Takumi NARUSE ,  Shuichiro YAMAGUCHI ,  Yoshinori HASHIMOTO

Inventor： Hiroshi KAWANO ,  Munenori FUJIMURA ,  Takumi NARUSE ,  Shuichiro YAMAGUCHI ,  Yoshinori HASHIMOTO

IPC: H05K7/00 ,  H05B33/00 ,  H04B3/54

CPC classification number: H05K1/0243 ,  H01L2224/82047 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H04B3/54 ,  H04B3/56 ,  H04B2203/5483 ,  H04L27/2626 ,  H04L27/2647 ,  H05K1/112 ,  H05K1/186 ,  H05K3/4614 ,  H05K2201/09509 ,  H05K2201/0979 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10689 ,  H05K2203/061

Abstract: A circuit module is mounted with an IC that modulates and demodulates a multicarrier signal. The circuit module has a laminated board, which is provided internally with a plurality of conductive layers laminated having insulating layers in between, and an IC, which is provided with a plurality of ground terminals to be grounded. Of the plurality of conductive layers, a conductive layer provided proximate to the IC configures a ground layer electrically connected to the plurality of ground terminals.

Abstract translation: 电路模块安装有用于对多载波信号进行调制和解调的IC。 电路模块具有层叠板，其内部设置有层叠有绝缘层的多个导电层和设置有要接地的多个接地端子的IC。 在多个导电层中，靠近IC设置的导电层构成与多个接地端子电连接的接地层。

公开(公告)号：US07342801B2

公开(公告)日：2008-03-11

申请号：US10835251

申请日：2004-04-29

Applicant: Gregory M. Jandzio ,  Anders P. Pedersen ,  Gary A. Rief ,  Walter M. Whybrew

Inventor： Gregory M. Jandzio ,  Anders P. Pedersen ,  Gary A. Rief ,  Walter M. Whybrew

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0243 ,  H01Q3/26 ,  H01Q21/0006 ,  H01Q21/0037 ,  H05K3/429 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/10553 ,  H05K2203/049 ,  Y10T29/49165

Abstract: A structural printed wiring board panel includes a multilayer printed wiring board having opposing, outer faces and interlayer interconnects that route RF, power and control signals. Connection areas are formed in or on at least on one face for connecting the interlayer interconnects and any electrical components. A metallic face sheet is secured onto at least one outer face, adding structural rigidity to the multilayer printed wiring board. A metallic face sheet can have apertures positioned to allow access to connection areas. RF components can be carried by a face sheet and operatively connected to connection areas. Antenna elements can be positioned on the same or an opposing face sheet and operatively connected to RF components to form a phased array printed wiring board (PWB) panel.

Abstract translation: 结构印刷线路板面板包括具有相对的外表面和层间互连的多层印刷线路板，其布置RF，功率和控制信号。 连接区域形成在至少一个面上或之上，用于连接层间互连和任何电气部件。 将金属面板固定在至少一个外表面上，为多层印刷线路板增加结构刚性。 金属面板可以具有定位成允许接近连接区域的孔。 RF部件可以由面板承载并且可操作地连接到连接区域。 天线元件可以定位在相同或相对的面板上并且可操作地连接到RF部件以形成相控阵列印刷线路板（PWB）面板。

公开(公告)号：US07339281B2

公开(公告)日：2008-03-04

申请号：US11139210

申请日：2005-05-26

Applicant: Ryosuke Usui ,  Hiroyuki Watanabe ,  Takeshi Nakamura

Inventor： Ryosuke Usui ,  Hiroyuki Watanabe ,  Takeshi Nakamura

IPC: H01L23/29

CPC classification number: H05K3/4655 ,  H01L21/565 ,  H01L23/4334 ,  H01L23/49531 ,  H01L23/5384 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2221/68377 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/0035 ,  H05K3/284 ,  H05K3/421 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/09509 ,  H05K2201/09581 ,  H05K2201/096 ,  H05K2203/0369 ,  H05K2203/0554 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A circuit device which enables easy formation of a connection part that connects wiring layers to each other, and a manufacturing method thereof are provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first resin film is formed so as to cover a first wiring layer. Thereafter, a first through-hole is formed, which penetrates the first resin film and exposes the first wiring layer from a bottom thereof. Next, a second resin film is formed so as to fill up the first through-hole. Moreover, a second through-hole is formed in the second resin film buried in the first through-hole, and a connection part is formed.

Abstract translation: 提供一种能够容易地形成将布线层彼此连接的连接部的电路装置及其制造方法。 在本发明的混合集成电路器件的制造方法中，形成第一树脂膜以覆盖第一布线层。 此后，形成穿过第一树脂膜并从其底部露出第一布线层的第一通孔。 接下来，形成第二树脂膜以填充第一通孔。 此外，在埋设在第一通孔中的第二树脂膜中形成第二通孔，形成连接部。

公开(公告)号：US07326858B2

公开(公告)日：2008-02-05

申请号：US10731246

申请日：2003-12-10

Applicant: Seok-Kyu Lee ,  Byoung-Youl Min ,  Hyun-Ju Jin ,  Jang-Kyu Kang

Inventor： Seok-Kyu Lee ,  Byoung-Youl Min ,  Hyun-Ju Jin ,  Jang-Kyu Kang

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09663 ,  H05K2201/09718

Abstract: Disclosed is a printed circuit board which is advantageous in terms of high capacitance by embedding capacitors comprising polymer capacitor pastes with high-dielectric constant coated on an inner layer of the printed circuit board and then semi-dried to a state of B-stage.

Abstract translation: 公开了一种印刷电路板，其通过将包含高介电常数的聚合物电容器浆料的电容器包埋在印刷电路板的内层上，然后半干燥至B级的状态而在高容量方面是有利的。

公开(公告)号：US20080026557A1

公开(公告)日：2008-01-31

申请号：US11868912

申请日：2007-10-10

Applicant: Peter Salmon

Inventor： Peter Salmon

IPC: H01L21/441

CPC classification number: H05K3/363 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05573 ,  H01L2224/11332 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/81052 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3651 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4015 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0568 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/05599

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server or supercomputer embodiment is also described.

Abstract translation: 本说明书描述了用于制造电子系统模块的技术。 该模块包括具有窄至5微米或更小的迹线宽度的柔性多层互连电路。 与用于制造液晶显示器，LCD，面板的玻璃面板制造设备相似，优选地用于制造互连电路。 使用剥离层在玻璃面板上制造多层互连电路。 在互连电路上形成特殊的组装层，该电路包括在输入/输出（I / O）焊盘位置处形成有开口的厚电介质层。 使用刮刀将焊膏沉积在开口中以形成填充有焊料的孔。 IC芯片在I / O焊盘位置处设有金柱凸起，并且这些凸块插入孔中以形成倒装芯片连接。 IC芯片经过测试和返工。 相同的凹凸/连接可用于连接细间距电缆。 提供模块封装层用于密封和电磁屏蔽。 还描述了刀片服务器或超级计算机实施例。

公开(公告)号：US20070278654A1

公开(公告)日：2007-12-06

申请号：US11778155

申请日：2007-07-16

Applicant: Lisa Jimarez ,  Miguel Jimarez ,  Voya Markovich ,  Cynthia Milkovich ,  Charles Perry ,  Brenda Peterson

Inventor： Lisa Jimarez ,  Miguel Jimarez ,  Voya Markovich ,  Cynthia Milkovich ,  Charles Perry ,  Brenda Peterson

IPC: H01L23/29 ,  H01L21/56

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/3457 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/4605 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/015 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/10734 ,  H05K2203/061 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.

Abstract translation: 提供电子封装和制造电子封装的方法。 电介质材料层位于包括多个导电触点的衬底的第一表面上。 至少一个通孔形成在电介质材料层中，与多个导电触点中的至少一个对准。 导电材料位于基本上填充通孔的至少一个通孔中。 至少一个导电构件定位在通孔中的导电材料上并与导电材料电接触。 该电子封装提高了组件的现场使用寿命，该组件包括附接到衬底的第二表面的半导体芯片和附着到导电构件的印刷线路板。

公开(公告)号：US20070269588A1

公开(公告)日：2007-11-22

申请号：US11309852

申请日：2006-10-13

Applicant: Wen-Chin Lee ,  Cheng-Hsien Lin

Inventor： Wen-Chin Lee ,  Cheng-Hsien Lin

IPC: C23C18/31

CPC classification number: H05K3/0035 ,  H05K3/0038 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/0554 ,  H05K2203/108

Abstract: A method for forming stacked via-holes on a printed circuit board includes the steps of: providing a printed circuit board having a conductive trace formed on a side surface thereof; forming a first copper-clad laminate on the side surface having the conductive trace; forming a number of first copper micro-via in a copper layer of the first copper-clad laminate; forming a second copper-clad laminate on the surface of the copper layer having the first copper micro-via of the first copper-clad laminate; forming a number of second copper micro-via in a copper layer of the second copper-clad laminate by a first laser on the basis of the first copper micro-via, each second copper micro-via being located corresponding to its correspondingly first copper micro-via; and removing corresponding resin layer portions of the first and second copper-clad laminates, using a second laser, to yield the respective stacked via-holes.

Abstract translation: 一种在印刷电路板上形成堆叠的通孔的方法包括以下步骤：提供在其侧表面上形成有导电迹线的印刷电路板; 在具有导电迹线的侧表面上形成第一覆铜层压板; 在第一覆铜层压板的铜层中形成多个第一铜微通孔; 在具有第一覆铜层压板的第一铜微通孔的铜层的表面上形成第二覆铜层压板; 基于第一铜微通孔，通过第一激光在第二覆铜层压板的铜层中形成多个第二铜微通孔，每个第二铜微通孔对应于其相应的第一铜微通孔 -通过; 并使用第二激光器除去第一和第二覆铜层压板的相应树脂层部分，以产生相应的堆叠通孔。