公开(公告)号：US09773682B1

公开(公告)日：2017-09-26

申请号：US15201628

申请日：2016-07-05

申请人： UNITED MICROELECTRONICS CORP.

发明人： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC分类号： H01L21/3105 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L21/31053 ,  H01L21/31055 ,  H01L29/0653 ,  H01L29/7851

摘要： A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

公开(公告)号：US20170263715A1

公开(公告)日：2017-09-14

申请号：US15067540

申请日：2016-03-11

申请人： GLOBALFOUNDRIES INC.

发明人： Guillaume Bouche ,  Tuhin Guha Neogi ,  Sudharshanan Raghunathan ,  Andy Chi-Hung Wei ,  Jason Eugene Stephens ,  Vikrant Kumar Chauhan ,  David Michael Permana

IPC分类号： H01L29/40 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/49 ,  H01L21/311

CPC分类号： H01L29/401 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0273 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

摘要： At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.

公开(公告)号：US09735246B1

公开(公告)日：2017-08-15

申请号：US15152144

申请日：2016-05-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/15 ,  H01L21/336 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/4991 ,  C23C14/0652 ,  C23C14/081 ,  C23C14/083 ,  C23C14/588 ,  C23C16/345 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31055 ,  H01L21/32115 ,  H01L23/315 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78654 ,  H01L2029/42388

摘要： Transistors and method of forming he same include forming a fin on a bottom source/drain region having a channel region and a sacrificial region on the channel region. A gate stack is formed on sidewalls of the channel region. A gate conductor is formed in contact with the gate stack that has a top surface that meets a middle point of sidewalls of the sacrificial region. The sacrificial region is trimmed to create gaps above the gate stack. A top spacer is formed on the gate conductor having airgaps above the gate stack.

公开(公告)号：US09711409B2

公开(公告)日：2017-07-18

申请号：US14409527

申请日：2012-11-19

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Huilong Zhu

IPC分类号： H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/088

CPC分类号： H01L21/823431 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/31055 ,  H01L21/31111 ,  H01L27/0886 ,  H01L29/66795

摘要： A fin arrangement and a method for manufacturing the same are provided. An example method may include: patterning a substrate to form an initial fin on a selected area of the substrate; forming, on the substrate, a dielectric layer to substantially cover the initial fin, wherein a portion of the dielectric layer located on top of the initial fin has a thickness substantially less than that of a portion the dielectric layer located on the substrate; and etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion of the initial fin is used as a fin.

公开(公告)号：US20170200714A1

公开(公告)日：2017-07-13

申请号：US15471693

申请日：2017-03-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC分类号： H01L27/06 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

CPC分类号： H01L29/66795 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66553

摘要： A method for forming a semiconductor device includes depositing a dielectric layer over fins formed in a semiconductor substrate. The dielectric layer includes a screen layer over tops of the fins. An etch stop feature is formed on the screen layer. The etch stop feature is patterned down to the screen layer in regions across the device. A dummy gate material formed over the fins is planarized down to the etch stop feature, a dielectric fill between gate structures patterned from the dummy gate material is planarized down to the etch stop feature and a gate conductor is planarized to the etch stop feature.

公开(公告)号：US20170170110A1

公开(公告)日：2017-06-15

申请号：US14970242

申请日：2015-12-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Chung-Ju Lee ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L23/528 ,  H01L21/321 ,  H01L21/3105 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L21/3212 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76808 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226

摘要： A method includes forming a trench that is partially filled with a first metal material, the trench being formed within a first Interlayer Dielectric (ILD) layer, filling a remaining portion of the trench with a sacrificial material, depositing a buffer layer on the first ILD layer, patterning the buffer layer to form a hole within the buffer layer to expose the sacrificial material, and removing the sacrificial material.

公开(公告)号：US20170166778A1

公开(公告)日：2017-06-15

申请号：US15115747

申请日：2015-01-21

申请人： BASF SE

发明人： Michael LAUTER ,  Roland LANGE ,  Bastian Marten NOLLER ,  Max SIEBERT

IPC分类号： C09G1/02 ,  H01L21/321 ,  H01L21/3105 ,  C09K3/14

CPC分类号： C09G1/02 ,  C09G1/18 ,  C09K3/1409 ,  C09K3/1463 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/76224

摘要： A chemical mechanical polishing (CMP) composition comprising (A) Colloidal or fumed inorganic particles or a mixture thereof, (B) a poly (amino acid) and or a salt thereof, and (M) an aqueous medium.

公开(公告)号：US09653356B2

公开(公告)日：2017-05-16

申请号：US14822340

申请日：2015-08-10

申请人： GLOBALFOUNDRIES Inc.

发明人： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L27/088 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/417 ,  H01L21/8234

CPC分类号： H01L21/76897 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2221/1026 ,  H01L2221/1036

摘要： One illustrative method disclosed includes, among other things, forming a silicon dioxide etch stop layer on and in contact with a source/drain region and adjacent silicon nitride sidewall spacers positioned on two laterally spaced-apart transistors having silicon dioxide gate cap layers, performing a first etching process through an opening in a layer of insulating material to remove the silicon nitride material positioned above the source/drain region, performing a second etching process to remove a portion of the silicon dioxide etch stop layer and thereby expose a portion of the source/drain region, and forming a conductive self-aligned contact that is conductively coupled to the source/drain region.

公开(公告)号：US20170125302A1

公开(公告)日：2017-05-04

申请号：US15400643

申请日：2017-01-06

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Jay W. Strane

IPC分类号： H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76229 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795

摘要： A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

公开(公告)号：US09627246B2

公开(公告)日：2017-04-18

申请号：US14735359

申请日：2015-06-10

申请人： Microchip Technology Incorporated

发明人： Justin Hiroki Sato ,  Gregory Allen Stom

IPC分类号： H01L21/70 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/06 ,  H01L21/8234

CPC分类号： H01L21/76229 ,  H01L21/0217 ,  H01L21/30604 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0649

摘要： A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.