公开(公告)号：US20180108630A1

公开(公告)日：2018-04-19

申请号：US15625033

申请日：2017-06-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Toyohiro Aoki ,  Takashi Hisada ,  Eiji Nakamura

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/13 ,  H01L24/742 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/024 ,  H01L2224/0382 ,  H01L2224/03826 ,  H01L2224/03827 ,  H01L2224/0401 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11003 ,  H01L2224/11312 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13018 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81815 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01201

Abstract: Wafers include multiple bulk redistribution layers. A terminal contact pad is on a surface of one of the bulk redistribution layers. A final redistribution layer is formed on the surface and in contact with the terminal contact pad. The final redistribution layer is formed from a material other than a material of the plurality of bulk redistribution layers. A solder ball is formed on the terminal contact pad.

公开(公告)号：US20170256517A1

公开(公告)日：2017-09-07

申请号：US15506511

申请日：2015-06-29

Applicant: Heraeus Deutschland GmbH & Co. KG

Inventor： Ki Ho KIM ,  Yong-Deok TARK ,  Il Tae KANG ,  Byoung Gil KIM ,  Tae Yeop KIM

IPC: H01L23/00 ,  H01B1/02

CPC classification number: H01L24/43 ,  H01B1/02 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/4321 ,  H01L2224/43848 ,  H01L2224/43986 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/78301 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01201 ,  H01L2924/01202 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01045 ,  H01L2924/0102 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/013 ,  H01L2924/00015 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/01049 ,  H01L2924/01005 ,  H01L2224/05599

Abstract: A bonding wire and a method of manufacturing the bonding wire are provided. The bonding wire contains 90.0 to 99.0 wt % of silver (Ag); 0.2 to 2.0 wt % of gold (Au); 0.2 to 4.0 wt % of palladium (Pd), platinum (Pt), rhodium (Rh), or a combination thereof; 10 to 1000 ppm of dopants; and inevitable impurities. In the wire, the ratio of (a)/(b) is 3 to 5, in which (a) represents the amount of crystal grains having orientation in crystalline orientations in a wire lengthwise direction and (b) represents the amount of crystal grains having orientation in crystalline orientations in the wire lengthwise direction.

公开(公告)号：US20170200534A1

公开(公告)日：2017-07-13

申请号：US15325338

申请日：2015-04-28

Applicant: Heraeus Deutschland GmbH & Co. KG

Inventor： Eugen MILKE ,  Larbi AINOUZ ,  Peter PRENOSIL

IPC: H01B13/00 ,  B21C1/02 ,  C22C9/00 ,  C23C30/00 ,  H01B1/02 ,  C22F1/08

CPC classification number: H01B13/0006 ,  B21C1/02 ,  C22C9/00 ,  C22F1/008 ,  C22F1/08 ,  C23C30/005 ,  H01B1/026 ,  H01B13/0016 ,  H01B13/0036 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/4312 ,  H01L2224/4321 ,  H01L2224/4382 ,  H01L2224/43847 ,  H01L2224/43848 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45016 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45655 ,  H01L2224/45664 ,  H01L2224/45666 ,  H01L2224/45669 ,  H01L2224/45671 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2924/00011 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/01201 ,  H01L2924/01202 ,  H01L2924/01203 ,  H01L2924/01204 ,  H01L2924/01001 ,  H01L2924/01007 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01005 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/00 ,  H01L2924/206

Abstract: A process for manufacturing a bonding wire containing a core having a surface. The core contains ≧98.0% copper and has a cross sectional area of 75,00 to 600,000 μm2 and an elastic limit RP0.2 (yield strength) of 40 to 95 N/mm2. The process involves (a) providing a copper core precursor; (b) drawing the precursor until a final diameter of the wire core is reached; and (c) annealing the drawn wire at a minimum annealing temperature of 650 to 1000° C. through its entire cross section for a minimum annealing time of 4 seconds to 2 hours.

公开(公告)号：US20170186714A1

公开(公告)日：2017-06-29

申请号：US15456746

申请日：2017-03-13

Applicant: Mitsubishi Electric Corporation

Inventor： Yosuke NAKATA ,  Masayoshi TARUTANI

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/05 ,  H01L23/498 ,  H01L24/01 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/034 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/16113 ,  H01L2224/16245 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73251 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/07025 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01201 ,  H01L2924/01014

Abstract: A semiconductor device of the present invention includes a semiconductor element, a surface electrode formed on a surface of the semiconductor element, a metal film formed on the surface electrode so as to have a joining portion and a stress relieving portion formed so as to border on and surround the joining portion, solder joined to the joining portion while avoiding the stress relieving portion, and an external electrode joined to the joining portion through the solder.

公开(公告)号：US20160104687A1

公开(公告)日：2016-04-14

申请号：US14893789

申请日：2015-03-31

Applicant: NIPPON MICROMETAL CORPORATION ,  NIPPON STEEL & SUMIKIN MATERIALS CO. LTD.

Inventor： Takashi YAMADA ,  Daizo ODA ,  Ryo OISHI ,  Teruo HAIBARA ,  Tomohiro UNO

IPC: H01L23/00 ,  C22C5/06 ,  C22C5/08 ,  B21C1/00 ,  C22F1/14

CPC classification number: H01L24/45 ,  B21C1/00 ,  B21C1/003 ,  C22C5/06 ,  C22C5/08 ,  C22F1/00 ,  C22F1/14 ,  H01L24/43 ,  H01L2224/4321 ,  H01L2224/43848 ,  H01L2224/43986 ,  H01L2224/45012 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2924/00011 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/201 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/00 ,  H01L2924/01201 ,  H01L2924/01016 ,  H01L2924/01017 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/12044 ,  H01L2924/00015 ,  H01L2224/45664 ,  H01L2924/01049 ,  H01L2924/01045 ,  H01L2924/01004 ,  H01L2924/01005

Abstract: Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center and parallel to the wire longitudinal direction (wire center cross-section), there are no crystal grains with a ratio a/b of a long axis “a” and a short axis “b” of 10 or more and with an area of 15 μm2 or more (“fiber texture”), (2) when measuring a crystal direction in the wire longitudinal direction in the wire center cross-section, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 10% to less than 50%, and (3) when measuring a crystal direction in the wire longitudinal direction at the wire surface, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 70% or more. During the drawing step, a drawing operation with a rate of reduction of area of 15.5% or more is performed at least once. The final heat treatment temperature and the pre-final heat treatment temperature are made predetermined ranges.

Abstract translation: 用于半导体器件的接合线，其中通过（1）在包含线中心并且平行于线纵向（线中心横截面）的横截面中抑制倾斜故障和弹簧故障，不存在具有 长轴“a”的比率a / b和短轴“b”为10以上，面积为15μm2以上（“纤维织构”），（2）当测定线材纵向的晶体方向 线中心横截面的方向，晶体方向<100>相对于导线纵向方向的角度差为15°以下的面积比为10％以上且小于50％，（3 ）当在线表面测量线长度方向的晶体方向时，晶体方向<100>与线长度方向的角度差为15°以下的面积比为70％以上 。 在拉伸步骤中，至少进行一次具有15.5％以上的面积减小率的拉拔操作。 将最终的热处理温度和预热处理温度设定为预定范围。

公开(公告)号：US20150262963A1

公开(公告)日：2015-09-17

申请号：US14724661

申请日：2015-05-28

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Kenichi KOYA ,  Isamu YONEKURA ,  Daisuke FUKAMACHI ,  Shinya HARANO

IPC: H01L23/00

CPC classification number: H01L24/48 ,  H01L24/45 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4845 ,  H01L2224/48455 ,  H01L2224/48465 ,  H01L2224/48479 ,  H01L2224/48482 ,  H01L2224/48997 ,  H01L2224/49 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/351 ,  H01L2224/48471 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85181 ,  H01L2924/20752 ,  H01L2924/01201 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01046 ,  H01L2924/01044 ,  H01L2924/01076 ,  H01L2924/01045 ,  H01L2924/01077 ,  H01L2924/0102 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01063 ,  H01L2924/01004 ,  H01L2924/01032 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/013 ,  H01L2224/43848 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A first bond portion is formed on a first electrode, and for a wire extended from the first bond portion, a tip of a capillary is pressed against a bump formed on a second electrode, to form a second bond portion to which a shape of a pressing surface at the tip of the capillary is transferred. A base end of the second bond portion from which the wire starts becoming thinner is located on the inside of the bump from an end of a bonding surface by 10% or more of the length of the bonding surface, and the wire is cut with the capillary.

Abstract translation: 第一接合部分形成在第一电极上，并且对于从第一接合部分延伸的电线，将毛细管的尖端压在形成在第二电极上的凸块上，形成第二接合部分， 毛细管尖端的按压面被传送。 电线开始变薄的第二接合部的基端从接合面的端部位于凸块的内侧，接合面的长度的10％以上，线被切断 毛细管。

公开(公告)号：US09123526B2

公开(公告)日：2015-09-01

申请号：US14144192

申请日：2013-12-30

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Xaver Schloegel ,  Khai Huat Jeffrey Low ,  Chee Soon Law

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00

CPC classification number: H01L23/49503 ,  B81C1/00301 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/00 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/84 ,  H01L24/85 ,  H01L24/91 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/37144 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45624 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73213 ,  H01L2224/78301 ,  H01L2224/7865 ,  H01L2224/84801 ,  H01L2224/85045 ,  H01L2224/85099 ,  H01L2224/851 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85801 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2924/01016 ,  H01L2924/01026 ,  H01L2924/01201

Abstract: A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element.

Abstract translation: 模块包括具有至少第一端子接触表面和第二端子接触表面的半导体芯片。 由基于Cu的材料制成的第一接合元件附接到第一端子接触表面，并且第二接合元件附接到第二端子接触表面。 第二结合元件由与第一结合元件的材料不同的材料制成，或者由不同于第一粘结元件的类型的粘结元件制成。

公开(公告)号：US20150235925A1

公开(公告)日：2015-08-20

申请号：US14422573

申请日：2012-09-04

Applicant: Yosuke Nakata ,  Masayoshi Tarutani

Inventor： Yosuke Nakata ,  Masayoshi Tarutani

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/498 ,  H01L24/01 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/034 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/16113 ,  H01L2224/16245 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73251 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/07025 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01201 ,  H01L2924/01014

Abstract: A semiconductor device of the present invention includes a semiconductor element, a surface electrode formed on a surface of the semiconductor element, a metal film formed on the surface electrode so as to have a joining portion and a stress relieving portion formed so as to border on and surround the joining portion, solder joined to the joining portion while avoiding the stress relieving portion, and an external electrode joined to the joining portion through the solder.

Abstract translation: 本发明的半导体器件包括半导体元件，形成在半导体元件的表面上的表面电极，形成在表面电极上的金属膜，以具有形成为接合部分的接合部分和应力消除部分 并且围绕接合部分，焊料接合到接合部分同时避免应力消除部分，以及外部电极通过焊料接合到接合部分。

公开(公告)号：US20150137390A1

公开(公告)日：2015-05-21

申请号：US14399003

申请日：2013-05-07

Applicant: Heraeus Materials Technology GmbH & Co. KG

Inventor： Eugen Milke ,  Peter Prenosil ,  Sven Thomas

IPC: H01L23/00 ,  H01L25/07 ,  B21C1/00 ,  H01L25/16 ,  B32B15/01 ,  B21C9/00

CPC classification number: H01L24/48 ,  B21C1/003 ,  B21C9/00 ,  B32B15/01 ,  H01B1/023 ,  H01B1/026 ,  H01L24/43 ,  H01L24/45 ,  H01L24/85 ,  H01L25/072 ,  H01L25/165 ,  H01L2224/43 ,  H01L2224/4321 ,  H01L2224/4382 ,  H01L2224/43848 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45033 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45624 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/45669 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/01322 ,  H01L2924/1203 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/16151 ,  H01L2924/20303 ,  H01L2924/20304 ,  H01L2924/20305 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/207 ,  H01L2924/2075 ,  Y10T29/49117 ,  Y10T428/1275 ,  H01L2924/01028 ,  H01L2924/01014 ,  H01L2924/01012 ,  H01L2924/01008 ,  H01L2924/01205 ,  H01L2924/01204 ,  H01L2924/01203 ,  H01L2924/01201 ,  H01L2924/01206 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2224/05599 ,  H01L2924/00013 ,  H01L2924/01049

Abstract: A ribbon, preferably a bonding ribbon for bonding in microelectronics, contains a first layer containing copper, a coating layer containing aluminum superimposed over the first layer, and an intermediate layer. In a cross-sectional view of the ribbon, the area share of the first layer is from 50 to 96% and the aspect ratio between the width and the height of the ribbon in a cross-sectional view is from 0.03 to less than 0.8. The ribbon has a cross-sectional area of 25,000 μm2 to 800,000 μm2. The intermediate layer contains at least one intermetallic phase containing materials of the first and coating layers. The invention further relates to a process for making a wire, to a wire obtained by the process, to an electric device containing the wire, to a propelled device comprising said electric device and to a process of connecting two elements through the wire by wedge-bonding.

Abstract translation: 带，优选用于在微电子学中结合的粘合带包含含有铜的第一层，包含叠加在第一层上的铝的涂层和中间层。 在带的横截面视图中，第一层的面积份额为50至96％，横截面视图中的带的宽度和高度之间的纵横比为0.03至小于0.8。 带的截面积为25,000μm2至800,000μm2。 中间层含有至少一种包含第一层和涂层的材料的金属间相。 本发明还涉及一种用于将由该工艺获得的线材制成的线材制造到包含该线材的电气装置的方法，该方法包括所述电气装置的推进装置以及通过楔形连接器将两个元件通过导线连接的过程， 粘接。

公开(公告)号：US08987910B2

公开(公告)日：2015-03-24

申请号：US13996555

申请日：2011-12-16

Applicant: Mustafa Özkök ,  Gustavo Ramos ,  Arnd Kilian

Inventor： Mustafa Özkök ,  Gustavo Ramos ,  Arnd Kilian

IPC: H01L23/48 ,  H01L21/44 ,  H05K13/04 ,  H01L23/498 ,  H05K3/24 ,  H01L23/00 ,  H01B1/02 ,  H05K1/09

CPC classification number: H05K13/04 ,  H01B1/02 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/03464 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05464 ,  H01L2224/05664 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/48664 ,  H01L2224/48864 ,  H01L2224/85045 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/85205 ,  H01L2224/85464 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/20105 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/09 ,  H05K3/244 ,  H05K2203/049 ,  H05K2203/072 ,  H05K2203/095 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/01201 ,  H01L2924/01202 ,  H01L2924/01203 ,  H01L2924/01005 ,  H01L2924/20752 ,  H01L2924/01007 ,  H01L2924/01001

Abstract: The present invention relates to a method of bonding a copper wire to a substrate, particularly a printed circuit board and an IC-substrate, possessing a layer assembly comprising a copper bonding portion and a palladium or palladium alloy layer and a substrate having a copper wire bonded to aforementioned layer assembly.

Abstract translation: 本发明涉及一种将铜线结合到具有包括铜结合部分和钯或钯合金层的层组件的基板，特别是印刷电路板和IC基板的方法，以及具有铜线的基板 粘合到上述层组件。