公开(公告)号：US20070035005A1

公开(公告)日：2007-02-15

申请号：US11200044

申请日：2005-08-10

Applicant: Paul Brown

Inventor： Paul Brown

IPC: H01L23/48

CPC classification number: H05K1/114 ,  H01L21/50 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K3/429 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/097 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A printed circuit board (PCB) assembly having a plurality of circuit layers including outer layers and intervening layers with through-vias and micro-vias used to translate a portion of the signal connections of the grid, thereby creating a set of diagonal routing channels between the vias on internal layers of the board and a BGA package mounted on the printed circuit board.

Abstract translation: 一种具有多个电路层的印刷电路板（PCB）组件，其包括外层和具有通孔和微通孔的中间层，其用于平移网格的信号连接的一部分，由此产生一组对角线路由信道， 板上内部的通孔和安装在印刷电路板上的BGA封装。

公开(公告)号：US07176052B2

公开(公告)日：2007-02-13

申请号：US11068884

申请日：2005-03-02

Applicant: Hiroko Koike ,  Takashi Mochizuki ,  Mitsutoshi Higashi

Inventor： Hiroko Koike ,  Takashi Mochizuki ,  Mitsutoshi Higashi

IPC: H01L51/40 ,  H01L21/8242

CPC classification number: H01L23/49822 ,  H01G9/15 ,  H01L21/4857 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0317 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2203/0315 ,  Y10S438/957 ,  Y10T29/417 ,  H01L2924/00

Abstract: A method of formation of a capacitor forming part of an electric circuit when producing a circuit board, consisting of forming a valve metal bottom electrode layer and a valve metal oxide dielectric layer on the same, then integrally forming a solid electrolyte layer comprised of an organic semiconductor and a top electrode layer comprised of metal on the same, this integral formation step consisting of the step of holding one surface of metal foil for the top electrode at a bonding wedge and making the other surface of the metal foil carry a powder of the organic semiconductor by compression bonding and heating and the step of compression bonding the organic semiconductor powder carried by compression bonding at the dielectric layer by a bonding wedge through metal foil, whereby a solid electrolyte layer comprised of an organic semiconductor sandwiched between the metal foil and dielectric layer and closely bonded with the two is formed, a capacitor built into a circuit board, a circuit board including a capacitor, and a method of production of the circuit board.

Abstract translation: 一种电容器形成电容器的形成方法，其特征在于，在制造电路基板时形成电路的一部分，其特征在于，在其上形成阀金属底电极层和阀金属氧化物电介质层，然后一体地形成由有机物构成的固体电解质层 半导体和由其上的金属组成的顶部电极层，该整体形成步骤包括将一个金属箔的表面保持在键合楔形件的顶部电极的一个表面，并使金属箔的另一个表面携带 通过压接和加热的有机半导体，以及通过金属箔通过接合楔将电介质层压接的有机半导体粉末压接的步骤，由此夹在金属箔和电介质之间的有机半导体构成的固体电解质层 形成两层紧密结合的电容器，内置于电路板的电容器，电路 其电路板包括电容器，以及生产电路板的方法。

公开(公告)号：US20070011871A1

公开(公告)日：2007-01-18

申请号：US11533919

申请日：2006-09-21

Applicant: Takashi HASHIMOTO

Inventor： Takashi HASHIMOTO

IPC: H05K3/10

CPC classification number: H05K3/4614 ,  H05K1/0306 ,  H05K3/125 ,  H05K3/1275 ,  H05K3/207 ,  H05K3/386 ,  H05K3/4069 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09981 ,  H05K2203/013 ,  H05K2203/0534 ,  H05K2203/061 ,  H05K2203/063 ,  H05K2203/1173 ,  Y10T29/49002 ,  Y10T29/49073 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49162 ,  Y10T29/49169 ,  Y10T29/49224

Abstract: Wirings 2B1 are formed by application of heat treatment after an ink jet system is used to discharge a conductive liquid L onto a provisional substrate 5 having a predetermined repellent property, bonding an insulating layer 4B1 to the wirings 2B1 with an adhesive material 3B1 therebetween, peeling and removing the provisional substrate 5, and bonding and fixing the wirings 2B1 together with the insulating film 4B1 to a main substrate 1 by an adhesive material 3B1.

Abstract translation: 在使用喷墨系统将导电液体L排出到具有预定排斥性的临时基板5上之后，通过施加热处理形成布线2B1，将绝缘层4B1与布线2B1接合 粘合材料3B 1，剥离和去除临时基板5，并且通过粘合剂材料3B B1将布线2B 1与绝缘膜4B 1一起粘合并固定到主基板1。

公开(公告)号：US07163841B2

公开(公告)日：2007-01-16

申请号：US11179431

申请日：2005-07-11

Applicant: Sadamichi Takakusaki ,  Yusuke Igarashi ,  Motoichi Nezu ,  Takaya Kusabe

Inventor： Sadamichi Takakusaki ,  Yusuke Igarashi ,  Motoichi Nezu ,  Takaya Kusabe

IPC: H01L21/49

CPC classification number: H05K3/4647 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0265 ,  H05K1/185 ,  H05K1/187 ,  H05K3/06 ,  H05K3/20 ,  H05K3/423 ,  H05K3/4652 ,  H05K3/4658 ,  H05K3/4682 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09736 ,  H05K2203/0152 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: To provide a method of manufacturing a highly reliable circuit device realizing a smaller, thinner and lighter configuration. In the method of manufacturing a circuit device according to the invention, a resin sealed body is separated from a supporting substrate, after the resin sealed body containing a circuit device is formed on a top surface of the supporting substrate. Therefore, manufacture of a circuit device having no substrate becomes possible and it realizes a thinner and lighter circuit device with improved heat dissipation. Moreover, since sealing with a sealing resin can be performed on the supporting substrate, warps, caused by the differences in thermal expansion coefficients between the sealing resin and conductive patterns and between the sealing resin and circuit components, can be prevented. Hence, it becomes possible to prevent flaking of conductive patterns from the substrate and a poor contact between the conductive patterns and a metal thin wire, and consequently to manufacture a highly reliable circuit device.

Abstract translation: 提供一种制造高可靠性电路装置的方法，其实现更小，更薄和更轻的构造。 在根据本发明的电路装置的制造方法中，在支撑基板的顶表面上形成包含电路装置的树脂密封体之后，树脂密封体与支撑基板分离。 因此，可以制造没有基板的电路装置，并且实现了具有改善的散热的更薄更轻的电路装置。 此外，由于可以在支撑基板上进行密封树脂的密封，所以可以防止由密封树脂和导电图案之间以及密封树脂和电路部件之间的热膨胀系数的差异引起的翘曲。 因此，可以防止导电图案从基板剥落，并且导电图案与金属细线之间的接触不良，从而制造高可靠性的电路装置。

公开(公告)号：US07152318B2

公开(公告)日：2006-12-26

申请号：US10603764

申请日：2003-06-26

Applicant: Bong-Suck Kim ,  Gye-Soo Kim ,  Jong-Hyung Kim ,  Il-Woon Shin

Inventor： Bong-Suck Kim ,  Gye-Soo Kim ,  Jong-Hyung Kim ,  Il-Woon Shin

IPC: H01K3/10

CPC classification number: H05K3/421 ,  H05K1/115 ,  H05K3/0035 ,  H05K2201/0215 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/025 ,  H05K2203/0554 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A built-up printed circuit board includes stacked micro via-holes, each of which is provided for interconnection between layers in the printed circuit board, and in each of which a filling material, such as liquefied resin or conductive paste, is filled using a poly screen of a general screen printing machine.

Abstract translation: 积层印刷电路板包括堆叠的微通孔，每个微通孔被设置用于印刷电路板中的层之间的互连，并且其中每个通孔使用诸如液化树脂或导电浆料填充材料 一般丝网印刷机的多屏。

公开(公告)号：US07138068B2

公开(公告)日：2006-11-21

申请号：US11084938

申请日：2005-03-21

Applicant: Gregory J. Dunn ,  Robert T. Croswell ,  Jaroslaw A. Magera ,  Jovica Savic ,  Aroon V. Tungare

Inventor： Gregory J. Dunn ,  Robert T. Croswell ,  Jaroslaw A. Magera ,  Jovica Savic ,  Aroon V. Tungare

IPC: H01L21/302

CPC classification number: C23F1/40 ,  C23F1/02 ,  C23F1/32 ,  C23F1/34 ,  H05K1/162 ,  H05K3/0044 ,  H05K3/025 ,  H05K3/06 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2203/025 ,  H05K2203/0746

Abstract: A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.

公开(公告)号：US20060254052A1

公开(公告)日：2006-11-16

申请号：US11482813

申请日：2006-07-10

Applicant: Shigeki Miura

Inventor： Shigeki Miura

IPC: H05K3/10 ,  C23C18/00

CPC classification number: H01L21/4846 ,  H01L21/4864 ,  H05K3/108 ,  H05K3/381 ,  H05K3/388 ,  H05K3/423 ,  H05K3/426 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2203/092 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A conductive sheet according to the present invention includes: an insulating substrate having at least one via hole, a ground conductive layer; and a top conductive layer, and characterized in that the via hole is a fine pore penetrating through the insulating substrate, the ground conductive layer is formed by a sputtering method or a vapor deposition method on all of a surface of the insulating substrate, the top conductive layer is formed on all of or part of a surface of the ground conductive layer, and the via hole is filled with the top conductive layer.

Abstract translation: 根据本发明的导电片包括：具有至少一个通孔的绝缘基底，接地导电层; 和导电层，其特征在于，所述通孔是穿过所述绝缘基板的细孔，所述接地导电层通过溅射法或气相沉积法形成在所述绝缘基板的所有表面上，所述顶部 导电层形成在接地导电层的表面的全部或一部分上，并且通孔填充有顶部导电层。

公开(公告)号：US07132357B2

公开(公告)日：2006-11-07

申请号：US11238894

申请日：2005-09-29

Applicant: Jeffrey A. Underwood ,  John K. Arledge ,  Thomas J. Swirbel ,  Joaquin Barreto

Inventor： Jeffrey A. Underwood ,  John K. Arledge ,  Thomas J. Swirbel ,  Joaquin Barreto

IPC: H01L21/44

CPC classification number: H05K1/0218 ,  H01L2223/6622 ,  H05K1/0221 ,  H05K1/0222 ,  H05K1/113 ,  H05K3/4644 ,  H05K9/0039 ,  H05K2201/0715 ,  H05K2201/09036 ,  H05K2201/09509 ,  H05K2201/09809 ,  H05K2201/09972 ,  H05K2201/09981 ,  H05K2201/10553 ,  H05K2201/10969 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method for shielding one or more circuits (21, 21′) of a printed circuit board includes depositing a layer of dielectric material (43) over a printed circuit board substrate (22) and the printed circuits (21, 21′), creating a trench-like opening (44) in the dielectric layer (43) such that the trench-like opening (44) surrounds the one or more circuits (21, 21′) to be shielded, depositing a layer of metal (27) over the layer of dielectric material (43) and within the trench-like openings (44), creating a solder pad (24) at each location where an electrical connection is to be made to the printed circuits (21, 21′) by removing a border of the metal layer (27) surrounding each connection location, and providing a microvia (25) through each solder pad (24) penetrating the dielectric layer (43) and terminating at the metal of the printed circuit (21, 21′).

公开(公告)号：US20060220167A1

公开(公告)日：2006-10-05

申请号：US11095690

申请日：2005-03-31

Applicant: Yongki Min ,  Islam Salama

Inventor： Yongki Min ,  Islam Salama

IPC: B32B37/00 ,  H01L21/00

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H05K1/112 ,  H05K1/162 ,  H05K3/16 ,  H05K3/382 ,  H05K3/4602 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T156/10 ,  H01L2224/0401

Abstract: A method of fabricating an integrated circuit package, comprising prefabricating a film capacitor including forming a first conductive layer, depositing a dielectric layer on the first conductive layer, and depositing a second conductive layer on the dielectric layer; forming a substrate; and laminating the prefabricated film capacitor to the substrate.

Abstract translation: 一种制造集成电路封装的方法，包括预制包括形成第一导电层的薄膜电容器，在所述第一导电层上沉积电介质层，以及在所述电介质层上沉积第二导电层; 形成基板; 并将预制的薄膜电容器层压到基板上。

公开(公告)号：US07100277B2

公开(公告)日：2006-09-05

申请号：US10882820

申请日：2004-07-01

Applicant: William J. Borland ,  Saul Ferguson ,  Hena Pyada

Inventor： William J. Borland ,  Saul Ferguson ,  Hena Pyada

IPC: H05K3/30 ,  H05K7/12

CPC classification number: H05K1/162 ,  H05K3/061 ,  H05K3/429 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of forming printed wiring boards having embedded thick-film capacitors includes covering capacitor layers with a protective coating prior to etching to prevent etching solutions from contacting with and damaging the capacitor layers and forming vias directly between the capacitor electrodes and the board circuitry.

Abstract translation: 形成具有嵌入式厚膜电容器的印刷电路板的方法包括在蚀刻之前用保护涂层覆盖电容器层，以防止蚀刻溶液与电容器层接触并损坏电容器层，并直接在电容器电极和电路板电路之间形成通孔。