公开(公告)号：US09281335B2

公开(公告)日：2016-03-08

申请号：US14494215

申请日：2014-09-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gianluca Testa ,  Giovanni De Amicis

IPC: H01L27/146 ,  H01L23/544

CPC classification number: H01L27/14634 ,  H01L23/544 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14687 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An imaging system may include an imager integrated circuit with frontside components such as imaging pixels and backside components such as color filters and microlenses. The imager integrated circuit may be mounted to a carrier wafer with alignment marks. Bonding marks on the carrier wafer and the imager integrated circuit may be used to align the carrier wafer accurately to the imager integrated circuit. The alignment marks on the carrier wafer may be read, by fabrication equipment, to align backside components of the imager integrated circuit, such as color filters and microlenses, with backside components of the imager integrated circuit, such as photodiodes.

Abstract translation: 成像系统可以包括具有前置部件的成像器集成电路，诸如成像像素和背面部件，例如滤色器和微透镜。 成像器集成电路可以安装到具有对准标记的载体晶片。 可以使用载体晶片和成像器集成电路上的接合标记将载体晶片与成像器集成电路精确对准。 可以通过制造设备读取载体晶片上的对准标记，以将成像器集成电路的背面部件（例如滤色器和微透镜）与成像器集成电路的背侧部件（例如光电二极管）对准。

公开(公告)号：US09241403B2

公开(公告)日：2016-01-19

申请号：US14090321

申请日：2013-11-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Gabriel Pares

IPC: H05K1/02 ,  H05K3/40 ,  H05K3/46 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498

CPC classification number: H05K1/0296 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02123 ,  H01L2224/02141 ,  H01L2224/0215 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0348 ,  H01L2224/036 ,  H01L2224/0381 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05584 ,  H01L2224/05644 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1148 ,  H01L2224/1181 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/16111 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/3201 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/00014 ,  H05K3/4084 ,  H05K3/467 ,  H01L2924/00015 ,  H01L2924/01047 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2224/051 ,  H01L2924/01074 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Forming of a microelectronic device including a substrate containing at least one conductive pad, the pad being provided with a bottom surface resting on the substrate and an upper surface opposite the bottom surface. The upper surface of the pad has a stack applied thereto formed of a conductive layer and a protective dielectric layer including an opening called first opening facing the pad and exposing the conductive layer. At least one insulating block is arranged on a peripheral region of the upper surface of the pad, the insulating block having a cross-section forming a closed contour and having an opening called second opening. A conductive pillar is located in the center of the contour in the second opening.

Abstract translation: 形成微电子器件，其包括含有至少一个导电焊盘的衬底，衬垫设置有搁置在衬底上的底表面和与底表面相对的上表面。 衬垫的上表面具有施加到其上的由导电层形成的叠层和保护电介质层，保护电介质层包括面向焊盘的称为第一开口的开口并暴露导电层。 至少一个绝缘块布置在垫的上表面的周边区域上，绝缘块具有形成闭合轮廓的横截面并且具有称为第二开口的开口。 导电柱位于第二开口中轮廓的中心。

公开(公告)号：US09219047B2

公开(公告)日：2015-12-22

申请号：US14168897

申请日：2014-01-30

Applicant: TOHOKU-MICROTEC CO., LTD

Inventor： Makoto Motoyoshi

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/14 ,  H01L23/498 ,  H01L23/544 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/14 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/02126 ,  H01L2224/0215 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/09517 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/1134 ,  H01L2224/11444 ,  H01L2224/1147 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/8109 ,  H01L2224/8114 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81986 ,  H01L2224/95146 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/01322 ,  H01L2924/15192 ,  H01L2924/00 ,  H01L2224/16225 ,  H01L2924/01013 ,  H01L2924/01032 ,  H01L2924/01051 ,  H01L2924/0105 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81

Abstract: A stacked device encompasses a lower chip including a plurality of wiring lands and a plurality of wall-block patterns, each of the wall-block patterns is allocated at a position except locations where the wiring lands are disposed, each of the wall-block patterns has a inclined plane, a height of each of the wall-block patterns measured from a reference plane of the array of the wiring lands is higher than the wiring lands, and an upper chip including a plurality of wiring bumps assigned correspondingly to the positions of the wiring lands, respectively, and a plurality of cone bumps assigned correspondingly to the positions of the wall-block patterns, respectively.

Abstract translation: 堆叠式装置包括包括多个布线平台和多个壁块图案的下部芯片，每个壁块图案被分配在除了设置布线平台的位置之外的位置处，每个壁块图案 具有倾斜平面，从布线平台的阵列的参考平面测量的每个壁块图案的高度高于布线平台，并且上部芯片包括相应于位置的多个布线凸块 分别布线着陆，以及分别对应于壁块图案的位置分配的多个锥形凸块。

公开(公告)号：US09209142B1

公开(公告)日：2015-12-08

申请号：US14562169

申请日：2014-12-05

Applicant: Skorpios Technologies, Inc.

Inventor： Damien Lambert ,  John Spann ,  Stephen Krasulick

IPC: H01L21/67 ,  H01L23/00 ,  H01L21/762 ,  H01L21/683 ,  H01L21/20

CPC classification number: H01L21/6835 ,  G02B6/4201 ,  H01L21/0274 ,  H01L21/2007 ,  H01L21/683 ,  H01L21/76254 ,  H01L24/03 ,  H01L24/27 ,  H01L24/75 ,  H01L24/83 ,  H01L24/89 ,  H01L24/94 ,  H01L24/95 ,  H01L2221/68313 ,  H01L2221/68318 ,  H01L2221/6834 ,  H01L2221/68354 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/0362 ,  H01L2224/75305 ,  H01L2224/75315 ,  H01L2224/80201 ,  H01L2224/83001 ,  H01L2224/83203 ,  H01L2225/06593 ,  H01L2924/01014 ,  H01L2924/1032 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15738

Abstract: A transfer substrate with a compliant resin is used to bond one or more chips to a target wafer. An implant region is formed in a transfer substrate. A portion of the transfer substrate is etched to form a riser. Compliant material is applied to the transfer substrate. A chip is secured to the compliant material, wherein the chip is secured to the compliant material above the riser. The chip is bonded to a target wafer while the chip is secured to the compliant material. The transfer substrate and compliant material are removed from the chip. The transfer substrate is opaque to UV light.

Abstract translation: 使用具有顺应性树脂的转印衬底将一个或多个芯片结合到目标晶片。 植入区域形成在转印衬底中。 转印衬底的一部分被蚀刻以形成提升器。 将合适的材料施加到转印基板上。 芯片被固定到柔性材料上，其中芯片被固定到提升管上方的柔性材料。 当芯片固定到顺应性材料时，芯片被结合到目标晶片。 从芯片上去除转印衬底和柔顺材料。 转印衬底对UV光是不透明的。

公开(公告)号：US20150348938A1

公开(公告)日：2015-12-03

申请号：US14737013

申请日：2015-06-11

Applicant: Terapede Systems Inc.

Inventor： Madhukar B. Vora

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L24/81 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L29/0657 ,  H01L2224/10165 ,  H01L2224/16238 ,  H01L2224/17515 ,  H01L2224/81001 ,  H01L2224/81002 ,  H01L2224/81005 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/00

Abstract: An electronic circuit and method may include a first chip including first electronics and a first connector including multiple self-alignment features and conductive pads. A second chip may include second electronics and a second connector including multiple self-alignment features and conductive pads. The first chip and second chip may be indirectly horizontally aligned with one another and in electrical communication with one another via the first and second connectors.

Abstract translation: 电子电路和方法可以包括包括第一电子器件的第一芯片和包括多个自对准特征和导电焊盘的第一连接器。 第二芯片可以包括第二电子器件和包括多个自对准特征和导电焊盘的第二连接器。 第一芯片和第二芯片可以间接地水平对准并且经由第一和第二连接器彼此电连通。

公开(公告)号：US20150333056A1

公开(公告)日：2015-11-19

申请号：US14280731

申请日：2014-05-19

Applicant: QUALCOMM Incorporated

Inventor： Yang Du ,  Karim Arabi

IPC: H01L27/06 ,  H01L21/50 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L25/0652 ,  H01L21/50 ,  H01L21/76895 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/83 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/0694 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/08146 ,  H01L2224/08147 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/83125 ,  H01L2224/83895 ,  H01L2224/9202 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/00014

Abstract: Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process.

Abstract translation: 公开了构造三维集成电路及相关系统的方法。 在一个方面，通过在保持基板上产生诸如晶体管的有源元件来构造第一层。 在有源元件上方形成互连金属层。 在互连金属层内形成金属焊盘。 也创建了第二层，并行或顺序。 第二层以与第一层大致相同的方式创建，然后被放置在第一层上，使得相应的金属焊盘对准并且被一层结合到另一层。 然后释放第二层的保持基板。 然后使第二层的背面变薄，使得有源元件的背面（例如，晶体管中的栅极的背面）被暴露。 如果需要，可以添加另外的层，基本上重复该过程。

公开(公告)号：US20150311186A1

公开(公告)日：2015-10-29

申请号：US14264699

申请日：2014-04-29

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Hong Wan Ng

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/0665

Abstract: Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.

Abstract translation: 本文公开了具有管芯支撑构件和相关联的系统和方法的堆叠的半导体管芯组件。 在一个实施例中，半导体管芯组件可以包括封装衬底，附接到封装衬底的第一半导体管芯和附接到封装衬底的支撑构件。 支撑构件可以与第一半导体管芯分离，并且第二半导体管芯可以具有联接到支撑构件的一个区域和耦合到第一半导体管芯的另一个区域。

公开(公告)号：US20150311185A1

公开(公告)日：2015-10-29

申请号：US14264584

申请日：2014-04-29

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Seng Kim Ye

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1205 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15174 ,  H01L2924/15182 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.

Abstract translation: 本文公开了具有支撑构件和相关系统和方法的堆叠的半导体管芯组件。 在一个实施例中，半导体管芯组件可以包括封装衬底，附接到封装衬底的第一半导体管芯，以及也附接到封装衬底的多个支撑构件。 多个支撑构件可以包括第一支撑构件和设置在第一半导体管芯的相对侧的第二支撑构件，并且第二半导体管芯可以联接到支撑构件，使得第二半导体管芯的至少一部分 在第一个半导体芯片上。

公开(公告)号：US09111946B2

公开(公告)日：2015-08-18

申请号：US13722340

申请日：2012-12-20

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed

IPC: H01L21/00 ,  H01L21/56 ,  H01L21/50 ,  H01L21/304 ,  H01L21/78 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/56 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/50 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A first area of a first surface of an encapsulated component can be thinned, the component including: a semiconductor chip having an active surface opposite the first surface, and an encapsulant extending outwardly from edges of the semiconductor chip. An entire area of the active surface may be aligned with the first area. After the abrading, a second area of the encapsulated component beyond the first area may have a thickness greater than a thickness of the first area. The second area can be configured to fully support the abraded encapsulated component in a state of the encapsulated component being manipulated by handling equipment.

Abstract translation: 封装部件的第一表面的第一区域可以变薄，所述部件包括：具有与第一表面相对的有效表面的半导体芯片以及从半导体芯片的边缘向外延伸的密封剂。 有源表面的整个区域可以与第一区域对齐。 在研磨之后，超过第一区域的包封组分的第二区域可以具有大于第一区域的厚度的厚度。 第二区域可以被配置为在被处理设备操纵的封装部件的状态下完全支撑磨损的封装部件。

公开(公告)号：US09111943B2

公开(公告)日：2015-08-18

申请号：US12725754

申请日：2010-03-17

Applicant: Eugene M. Chow ,  Philipp H. Schmaelzle

Inventor： Eugene M. Chow ,  Philipp H. Schmaelzle

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/544 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/11013 ,  H01L2224/11015 ,  H01L2224/11848 ,  H01L2224/1301 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13078 ,  H01L2224/1319 ,  H01L2224/14179 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81897 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A multi-chip module (MCM) that includes alignment features is described. This MCM includes at least two substrates having facing surfaces with positive features disposed on them. Note that a given positive feature on either of the surfaces protrudes above the surface. Furthermore, the two substrates are mechanically coupled by these positive features. In particular, a given one of the positive features on one of the surfaces mates with a given subset of the positive features on the other of the surfaces. Additionally, the given subset of the positive features includes two or more of the positive features.

Abstract translation: 描述了包括对准特征的多芯片模块（MCM）。 该MCM包括具有设置在其上的具有正特征的面对表面的至少两个基板。 请注意，任一表面上的给定正面特征突出在表面上方。 此外，两个基板通过这些正特征机械耦合。 特别地，其中一个表面上的给定的一个正特征与另一个表面上的正特征的给定子集配合。 此外，正特征的给定子集包括两个或多个正特征。