公开(公告)号：US09538649B2

公开(公告)日：2017-01-03

申请号：US14199327

申请日：2014-03-06

申请人： Murata Manufacturing Co., Ltd.

发明人： Nobuaki Ogawa ,  Yoshihito Otsubo

IPC分类号： H05K3/30 ,  H05K1/11 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L23/552 ,  H01L25/065 ,  H05K3/46 ,  H01L23/538 ,  H05K3/40 ,  H05K3/28 ,  H05K1/18

CPC分类号： H05K1/11 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/5389 ,  H01L23/552 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/1531 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/181 ,  H05K3/284 ,  H05K3/303 ,  H05K3/4015 ,  H05K3/4046 ,  H05K3/4644 ,  H05K2201/0715 ,  H05K2201/10242 ,  H05K2201/1031 ,  H05K2201/10515 ,  H05K2203/1316 ,  Y02P70/611 ,  Y10T29/49146

摘要： When forming a module 100 having a configuration in which a column-shaped connection terminal 11, which forms an interlayer connection conductor, and an electronic component 102 are mounted on a wiring substrate 101 and sealed with a resin, the column-shaped connection terminal 11 which has a substantially T-shaped cross section and in which a first end portion has a larger diameter than a second end portion is prepared (the preparation step), an electronic component 102 is mounted on one main surface of the wiring substrate 101 and the connection terminal 11 is mounted on the one main surface in such a manner that the second end portion of the connection terminal 11 having a smaller diameter is connected to the wiring substrate 101 (the mounting step), and the electronic component 102 and the connection terminal 11 are sealed with a resin layer 103 (the sealing step).

摘要翻译： 当形成具有其中形成层间连接导体的柱状连接端子11和电子部件102的结构的模块100安装在布线基板101上并用树脂密封时，柱形连接端子11 其具有大致T形的横截面并且其中第一端部具有比第二端部更大的直径（制备步骤），电子部件102安装在布线基板101的一个主表面上，并且 连接端子11安装在一个主表面上，使得具有较小直径的连接端子11的第二端部连接到布线基板101（安装步骤），并且电子部件102和连接端子 11用树脂层103密封（密封步骤）。

公开(公告)号：US09468089B2

公开(公告)日：2016-10-11

申请号：US14460694

申请日：2014-08-15

申请人： Kabushiki Kaisha Toshiba

发明人： Tadahiro Sasaki ,  Hiroshi Yamada

IPC分类号： H04B3/28 ,  H05K1/02 ,  H01L23/00 ,  H01L23/498

CPC分类号： H05K1/0236 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2924/1531 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0225 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0242 ,  H05K1/0243 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09254 ,  H05K2201/0969 ,  H05K2201/09727

摘要： An EBG structure of an embodiment includes an electrode plane, a first insulating layer provided on the electrode plane, a first metal patch provided on the first insulating layer, a second metal patch provided on the first insulating layer, a second insulating layer provided on the first and second metal patches, an interconnect layer provided on the second insulating layer, a third insulating layer provided on the interconnect layer, a first via connected to the electrode plane and the first metal patch, and a second via connected to the electrode plane and the second metal patch. The second metal patch is separately adjacent to the first metal patch. The interconnect layer has a first opening and a second opening. The first via penetrates through the first opening. The second via penetrates through the second opening.

摘要翻译： 实施例的EBG结构包括电极平面，设置在电极平面上的第一绝缘层，设置在第一绝缘层上的第一金属贴片，设置在第一绝缘层上的第二金属贴片，设置在第一绝缘层上的第二绝缘层 第一和第二金属贴片，设置在第二绝缘层上的互连层，设置在互连层上的第三绝缘层，连接到电极平面和第一金属贴片的第一通孔，以及连接到电极平面的第二通孔和 第二个金属贴片。 第二金属贴片与第一金属贴片分开相邻。 互连层具有第一开口和第二开口。 第一个通孔穿过第一个开口。 第二通孔穿过第二开口。

公开(公告)号：US09414513B2

公开(公告)日：2016-08-09

申请号：US14576452

申请日：2014-12-19

申请人： Murata Manufacturing Co., Ltd.

发明人： Hideo Nakagoshi ,  Yoichi Takagi ,  Nobuaki Ogawa ,  Hidekiyo Takaoka ,  Kosuke Nakono ,  Akihiko Kamada ,  Masaaki Mizushiro

IPC分类号： H05K1/18 ,  H05K7/02 ,  H01L23/498 ,  H01L25/16 ,  H05K1/14 ,  H05K3/36 ,  H05K3/40 ,  H01L23/15 ,  H05K3/28

CPC分类号： H05K7/02 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49822 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2924/1531 ,  H01L2924/19106 ,  H05K1/141 ,  H05K1/186 ,  H05K3/284 ,  H05K3/368 ,  H05K3/4015 ,  H05K2201/0367 ,  H05K2201/10318 ,  H05K2201/10477 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K2203/047

摘要： A plating layer of a Cu-M-based alloy (M represents Ni and/or Mn) is formed on an end surface of a connection terminal member at an exposed side, the Cu-M-based alloy being capable of generating an intermetallic compound with an Sn-based low-melting-point metal contained in a bonding material forming a bonding portion and having a lattice constant different from that of the intermetallic compound by 50% or more. In the reflow process, even if the bonding material is about to flow out by re-melting thereof, since the bonding material is brought into contact with the Cu-M-based plating layer, a high-melting-point alloy of the intermetallic compound is formed so as to block the interface between the connection terminal member and the resin layer.

摘要翻译： 在暴露侧的连接端子构件的端面上形成Cu-M系合金的镀层（M表示Ni和/或Mn），Cu-M系合金能够产生金属间化合物 所述Sn基低熔点金属包含在形成接合部分并且具有不同于金属间化合物的晶格常数的接合材料中的50％以上。 在回流工序中，即使接合材料通过再熔化即将流出，由于接合材料与Cu-M系镀层接触，所以金属间化合物的高熔点合金 形成为阻挡连接端子构件和树脂层之间的界面。

公开(公告)号：US20160197063A1

公开(公告)日：2016-07-07

申请号：US15067203

申请日：2016-03-11

申请人： BRIDGE SEMICONDUCTOR CORPORATION

发明人： Charles W. C. Lin ,  Chia-Chung Wang

IPC分类号： H01L25/10 ,  H01L25/00

CPC分类号： H01L25/105 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/15793 ,  H01L2924/16153 ,  H01L2924/16172 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/16724 ,  H01L2924/16747 ,  H01L2924/1676 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by the step of attaching a chip-on-interposer subassembly on a metallic carrier with the chip inserted into a cavity of the metallic carrier, and the step of selectively removing portions of the metallic carrier to define a heat spreader for the chip. The heat spreader can provide thermal dissipation, electromagnetic shielding and moisture barrier, whereas the interposer provides a CTE-matched interface and fan-out routing for the chip.

公开(公告)号：US09349615B2

公开(公告)日：2016-05-24

申请号：US13883143

申请日：2010-12-30

申请人： Jianyou Xie ,  Xizhou Li ,  Wei Mu ,  Yongzhong Wang ,  Haidong Wei

发明人： Jianyou Xie ,  Xizhou Li ,  Wei Mu ,  Yongzhong Wang ,  Haidong Wei

IPC分类号： H01L29/00 ,  H01L21/56 ,  H01L25/065 ,  H01L27/04 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L21/565 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L27/04 ,  H01L2223/5442 ,  H01L2223/54486 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1531 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A system-in-package (SiP) system-integration integrated circuit (IC) chip package and a manufacturing method thereof are provided. The package includes a substrate, a passive device and two IC chips are provided on the substrate, an adhesive film is disposed between each of the two IC chips and the substrate, the IC chips are connected to first pads on the substrate through bonding wires, and the substrate is covered by a mold cap. A third IC chip may be further disposed on one of the IC chips, and the third IC chip is connected to the first pad and the IC chip under the third IC chip respectively through a bonding wire. A substrate adopting a surface mount technology (SMT) PAD window-opening manner is used, chip mounting is performed on the substrate, and the substrate undergoes reflow soldering, cleaning, die bonding, plasma cleaning, bonding, marking, cutting, and packing, so that the SiP system-integration IC chip package is manufactured. The package of the present invention integrates devices of different types, has a complete system function, and can be used as a middle stage of further development of system on chip (SoC).

摘要翻译： 提供一种系统级封装（SiP）系统集成电路（IC）芯片封装及其制造方法。 封装包括衬底，无源器件和两个IC芯片设置在衬底上，粘合膜设置在两个IC芯片和衬底之间，IC芯片通过接合线连接到衬底上的第一焊盘， 并且基板被模具盖覆盖。 第三IC芯片可以进一步设置在一个IC芯片上，并且第三IC芯片分别通过接合线连接到第三IC芯片下面的第一焊盘和IC芯片。 使用采用表面贴装技术（SMT）PAD开窗方式的基板，在基板上进行芯片安装，并且基板进行回流焊接，清洗，芯片接合，等离子体清洗，接合，标记，切割和封装， 从而制造SiP系统集成IC芯片封装。 本发明的封装集成了不同类型的器件，具有完整的系统功能，可以作为芯片（SoC）进一步开发的中间阶段。

公开(公告)号：US09332646B2

公开(公告)日：2016-05-03

申请号：US13745766

申请日：2013-01-19

申请人： UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD. ,  UNIVERSAL GLOBAL SCIENTIFIC INDUSTRIAL CO., LTD.

发明人： Jen-Chun Chen ,  Hsin-Chin Chang

IPC分类号： H05K1/18 ,  H05K3/30 ,  H01L23/552 ,  H01L25/16 ,  H05K3/28 ,  H01L23/31

CPC分类号： H05K1/186 ,  H01L23/3135 ,  H01L23/552 ,  H01L25/16 ,  H01L2224/48091 ,  H01L2924/0002 ,  H01L2924/1531 ,  H01L2924/181 ,  H05K3/284 ,  H05K3/30 ,  H05K2201/1056 ,  H05K2203/1316 ,  H05K2203/1327 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： An electronic package module includes a circuit board having a supporting surface, at least one first electronic component, at least one second electronic component, and at least one molding compound. The first and second electronic components are mounted on the supporting surface. The molding compound is disposed on the supporting surface and covers the supporting surface partially. The molding compound encapsulates the first electronic component yet not the second electronic component.

摘要翻译： 电子封装模块包括具有支撑表面的电路板，至少一个第一电子部件，至少一个第二电子部件和至少一个模制化合物。 第一和第二电子部件安装在支撑表面上。 模制化合物设置在支撑表面上并且部分地覆盖支撑表面。 模制化合物封装第一电子部件而不是第二电子部件。

公开(公告)号：US09301395B2

公开(公告)日：2016-03-29

申请号：US13728385

申请日：2012-12-27

申请人： NVIDIA Corporation

发明人： Tiecheng Liang

IPC分类号： G06F1/16 ,  H05K13/04 ,  H05K1/18 ,  H05K3/34 ,  H05K1/02 ,  H01G4/30 ,  H01G4/38 ,  H01G9/15 ,  H01G9/28 ,  H01G2/06 ,  H01L23/64

CPC分类号： H05K1/181 ,  H01G2/06 ,  H01G4/30 ,  H01G4/38 ,  H01G9/15 ,  H01G9/28 ,  H01L23/642 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1531 ,  H01L2924/19041 ,  H01L2924/19106 ,  H05K1/023 ,  H05K1/0243 ,  H05K3/341 ,  H05K2201/10015 ,  Y02P70/611 ,  Y10T29/4913

摘要： Disclosed are methods and systems to reduce voltage noise on a printed circuit board (PCB) through a co-layout of multilayer ceramic capacitors. In one or more embodiments, this surface mounted layout comprises a first co-layout of multilayer ceramic capacitors mounted on a first corner of a rectangular footprint of a bottom side of the PCB; a second co-layout of multilayer ceramic capacitors mounted on a second corner of the rectangular footprint diagonal to the first corner; and a first solid electrolytic polymer capacitor and a second solid electrolytic polymer capacitor mounted on the remaining corners, respectively, of the rectangular footprint. The rectangular footprint of the PCB is a footprint of a high-speed processing unit mounted on the PCB. The high-speed processing unit is mounted on a top side of the PCB opposite the bottom side comprising the first co-layout of multilayer ceramic capacitors and the second co-layout of multilayer ceramic capacitors.

摘要翻译： 公开了通过多层陶瓷电容器的共同布局来降低印刷电路板（PCB）上的电压噪声的方法和系统。 在一个或多个实施例中，该表面安装布局包括安装在PCB的底侧的矩形覆盖区的第一角上的多层陶瓷电容器的第一共同布局; 多层陶瓷电容器的第二共同布置，安装在与第一角的矩形脚印对角线的第二角上; 和第一固体电解聚合物电容器和第二固体电解聚合物电容器，其分别安装在矩形覆盖区的其余角上。 PCB的矩形占用面积是安装在PCB上的高速处理单元的占位面积。 高速处理单元安装在PCB的与底侧相对的顶侧，包括多层陶瓷电容器的第一共布局和多层陶瓷电容器的第二共布局。

公开(公告)号：US20160043813A1

公开(公告)日：2016-02-11

申请号：US14883399

申请日：2015-10-14

申请人： Skyworks Solutions, Inc.

发明人： Howard E. Chen ,  Matthew Sean Read ,  Hoang Mong Nguyen ,  Anthony James LoBianco ,  Guohao Zhang ,  Dinhphuoc Vu Hoang

IPC分类号： H04B15/02 ,  H01L23/552 ,  H01L23/522

CPC分类号： H04B15/02 ,  G06F17/5081 ,  H01L21/561 ,  H01L23/5226 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/1531 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01Q1/526 ,  H04B1/16 ,  H04B1/44 ,  H04B15/04 ,  H05K1/023 ,  H05K1/115 ,  H05K2201/09618 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00

摘要： Aspects of the present disclosure relate to determining the location and/or density of vias that form part of an RF isolation structure of a packaged module and the resulting RF isolation structures. From electromagnetic interference (EMI) data, locations of where via density can be increased and/or decreased without significantly degrading the EMI performance of the RF isolation structure can be identified. In certain embodiments, one or more vias can be added and/or removed from a selected area of the packaged module based on the EMI data.

摘要翻译： 本公开的方面涉及确定形成封装模块的RF隔离结构的一部分的通孔的位置和/或密度以及所得到的RF隔离结构。 可以从电磁干扰（EMI）数据中识别通过密度可以增加和/或减小的位置，而不会明显降低RF隔离结构的EMI性能。 在某些实施例中，可以基于EMI数据从封装模块的选定区域添加和/或移除一个或多个通孔。

公开(公告)号：US09252107B2

公开(公告)日：2016-02-02

申请号：US13904566

申请日：2013-05-29

申请人： Skyworks Solutions, Inc.

发明人： Matthew Sean Read ,  Hoang Mong Nguyen ,  Anthony James LoBianco ,  Howard E. Chen ,  Dinhphuoc Vu Hoang

IPC分类号： H01Q1/38 ,  H01L23/552 ,  H01Q1/52 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/552 ,  H01L21/563 ,  H01L21/565 ,  H01L23/66 ,  H01L24/27 ,  H01L24/32 ,  H01L24/97 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2223/6672 ,  H01L2224/29139 ,  H01L2224/29194 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/19107 ,  H01Q1/526 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00

摘要： Disclosed are devices and methods related to a conductive paint layer configured to provide radio-frequency (RF) shielding for a packaged semiconductor module. Such a module can include a packaging substrate, one or more RF components mounted on the packaging substrate, a ground plane disposed within the packaging substrate, and a plurality of RF-shielding wirebonds disposed on the packaging substrate and electrically connected to the ground plane. The module can further include an overmold structure formed over the packaging substrate and dimensioned to substantially encapsulate the RF component(s) and the RF-shielding wirebonds. The overmold structure can define an upper surface that exposes upper portions of the RF-shielding wirebonds. The module can further include a conductive paint layer having silver flakes disposed on the upper surface of the overmold structure so that the conductive paint layer, the RF-shielding wirebonds, and the ground plane form an RF-shield for the RF component(s).

摘要翻译： 公开了与导电涂料层相关的装置和方法，其被配置为为封装的半导体模块提供射频（RF）屏蔽。 这样的模块可以包括封装衬底，安装在封装衬底上的一个或多个RF组件，设置在封装衬底内的接地平面以及设置在封装衬底上并电连接到接地面的多个RF屏蔽线圈。 模块还可以包括形成在封装衬底上的包覆模制结构，其尺寸被设计成基本上封装RF部件和RF屏蔽线束。 包覆模制结构可以限定暴露RF屏蔽线束的上部的上表面。 模块还可以包括具有设置在包覆模制结构的上表面上的银薄片的导电涂料层，使得导电涂料层，RF屏蔽引线键和接地平面形成用于RF组件的RF屏蔽， 。

公开(公告)号：US09190211B2

公开(公告)日：2015-11-17

申请号：US14452595

申请日：2014-08-06

申请人： MURATA MANUFACTURING CO., LTD.

发明人： Seiji Fujita ,  Hiroshige Adachi ,  Kazuhiro Kaneko ,  Satoru Adachi ,  Sadaaki Sakamoto

IPC分类号： H01G4/10 ,  H01G4/12 ,  C04B35/20 ,  C04B35/443 ,  C04B35/462 ,  H01G4/30 ,  H01G4/40 ,  B32B18/00 ,  H01L23/552

CPC分类号： H01G4/129 ,  B32B18/00 ,  C03C3/064 ,  C03C12/00 ,  C03C14/004 ,  C04B35/20 ,  C04B35/443 ,  C04B35/462 ,  C04B2235/3206 ,  C04B2235/3215 ,  C04B2235/3222 ,  C04B2235/3224 ,  C04B2235/3232 ,  C04B2235/3262 ,  C04B2235/3281 ,  C04B2235/3445 ,  C04B2235/3481 ,  C04B2235/36 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/346 ,  C04B2237/62 ,  H01G4/105 ,  H01G4/12 ,  H01G4/1209 ,  H01G4/1218 ,  H01G4/30 ,  H01G4/40 ,  H01L23/552 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/19041 ,  H01L2924/19105

摘要： A composite laminated ceramic electronic component that includes co-fired low dielectric-constant ceramic layers and high dielectric-constant ceramic layers. The low dielectric-constant ceramic layers and high dielectric-constant ceramic layers are each composed of a glass ceramic containing: a first ceramic composed of MgAl2O4 and/or Mg2SiO4; a second ceramic composed of BaO, RE2O3 (RE is a rare-earth element), and TiO2; glass containing each of 44.0 to 69.0 weight % of RO (R is an alkaline-earth metal), 14.2 to 30.0 weight % of SiO2, 10.0 to 20.0 weight % of B2O3, 0.5 to 4.0 weight % of Al2O3, 0.3 to 7.5 weight % of Li2O, and 0.1 to 5.5 weight % of MgO; and MnO, and the content ratios of the glass, etc. are varied between the low dielectric-constant ceramic layers and the high dielectric-constant ceramic layers.

摘要翻译： 一种复合层压陶瓷电子元件，包括共烧低介电常数陶瓷层和高介电常数陶瓷层。 低介电常数陶瓷层和高介电常数陶瓷层各自由玻璃陶瓷组成，该陶瓷含有：由MgAl 2 O 4和/或Mg 2 SiO 4组成的第一陶瓷; 由BaO，RE2O3（RE为稀土元素）和TiO2组成的第二陶瓷; 含有44.0〜69.0重量％的RO（R为碱土金属），14.2〜30.0重量％的SiO 2，10.0〜20.0重量％的B 2 O 3，0.5〜4.0重量％的Al 2 O 3，0.3〜7.5重量％ 的Li 2 O和0.1〜5.5重量％的MgO; 和MnO，并且玻璃等的含量比在低介电常数陶瓷层和高介电常数陶瓷层之间变化。