公开(公告)号：US06891273B2

公开(公告)日：2005-05-10

申请号：US10404173

申请日：2003-04-01

申请人： Han-Ping Pu ,  Chien Ping Huang

发明人： Han-Ping Pu ,  Chien Ping Huang

IPC分类号： H01L21/60 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171

摘要： A semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a substrate, and a dielectric layer is applied over the substrate and chip, with bond fingers formed on the substrate and electric contacts formed on the chip being exposed outside. A metal layer is formed over the dielectric layer and the exposed bond fingers and electric contacts, and patterned to form a plurality of conductive traces that electrically connect the electric contacts of the chip to the bond fingers of the substrate. The conductive traces replace conventional wire bonding technology and thus eliminate the occurrence of wire sweep or short circuits in fabrication processes. Therefore, a low profile chip with a reduced pitch between adjacent electric contacts can be used without being limited to feasibility of the wire bonding technology.

摘要翻译： 提供了一种半导体封装及其制造方法，其中芯片安装在基板上，并且电介质层被施加在基板和芯片上，具有形成在基板上的结合指状物，并且形成在芯片上的电触点暴露在外部。 在电介质层和暴露的结合指状物和电触点之上形成金属层，并且被图案化以形成将芯片的电触头电连接到衬底的结合指的多个导电迹线。 导电迹线取代了传统的引线键合技术，从而消除了制造工艺中线扫或短路的发生。 因此，可以使用在相邻的电触点之间具有减小的间距的低轮廓芯片，而不限于引线接合技术的可行性。

公开(公告)号：US20050036291A1

公开(公告)日：2005-02-17

申请号：US10759863

申请日：2004-01-16

申请人： Chien-Ping Huang ,  Han-Ping Pu ,  Chin-Te Chen ,  Chang-Fu Lin

发明人： Chien-Ping Huang ,  Han-Ping Pu ,  Chin-Te Chen ,  Chang-Fu Lin

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/055 ,  H01L23/10 ,  H01L23/367 ,  H01L23/467 ,  H01L25/065 ,  H05K7/20

CPC分类号： H01L23/467 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/055 ,  H01L23/10 ,  H01L23/3672 ,  H01L23/3675 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/16315 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00

摘要： A semiconductor package with a heat dissipating structure includes a substrate, a chip and a heat dissipating structure. The chip is mounted on and electrically connected to the substrate. The heat dissipating structure includes a first heat sink having at least one positioning portion, and at least one second heat sink having at least one second positioning portion and at least one hollow portion. The second heat sink is mounted on the substrate, and the first positioning portion of the first heat sink is attached to the second positioning portion of the second heat sink, allowing the chip to be accommodated in a space defined by the first heat sink, the hollow portion of the second heat sink and the substrate. This semiconductor package has good heat dissipating efficiency and is cost-effective to fabricate.

摘要翻译： 具有散热结构的半导体封装包括基板，芯片和散热结构。 芯片安装在基板上并电连接到基板。 散热结构包括具有至少一个定位部分的第一散热器和具有至少一个第二定位部分和至少一个中空部分的至少一个第二散热器。 第二散热器安装在基板上，并且第一散热器的第一定位部分附接到第二散热器的第二定位部分，允许芯片容纳在由第一散热器限定的空间中， 第二散热器的中空部分和基板。 该半导体封装具有良好的散热效率，并且制造成本低。

公开(公告)号：US06593662B1

公开(公告)日：2003-07-15

申请号：US09631343

申请日：2000-08-02

申请人： Han-Ping Pu ,  Randy H. Y. Lo ,  Tzong-Dar Her ,  Chien-Ping Huang ,  Cheng-Shiu Hsiao ,  Chi-Chuan Wu

发明人： Han-Ping Pu ,  Randy H. Y. Lo ,  Tzong-Dar Her ,  Chien-Ping Huang ,  Cheng-Shiu Hsiao ,  Chi-Chuan Wu

IPC分类号： H01L2348

CPC分类号： H01L24/33 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A stacked-die package structure comprises a carrier, dies, spacers, adhesive layers, conductive lines, a mold compound, and solder balls. The carrier has an upper surface and a back surface opposite to the upper surface. The dies substantially having the same sizes are stacked one by one on the upper surface of the carrier, and a number of bonding pads are located around each die. The spacers are located between two adjacent dies. Adhesive layers located between the spacers, the dies, and the carrier for adhering layers therebetween. The conducting lines are respectively electrically connected between each of the bonding pads of the dies and the carrier. And the mold compound is formed over the upper surface of the carrier, for encapsulating the spacers, the dies and the adhesive layers. A substrate with solder balls or a lead frame having pins is suitable for serving as the carrier.

摘要翻译： 堆叠管芯封装结构包括载体，管芯，间隔物，粘合剂层，导电线，模具化合物和焊球。 载体具有与上表面相对的上表面和后表面。 基本上具有相同尺寸的模具在载体的上表面上一个接一个堆叠，并且多个焊盘位于每个管芯周围。 间隔件位于两个相邻的模具之间。 位于间隔件，模具和载体之间的粘合层，用于在其间粘合层。 导体线分别电连接在管芯和载体的每个接合焊盘之间。 并且模制化合物形成在载体的上表面上，用于封装间隔物，模具和粘合剂层。 具有焊球或具有引脚的引线框架的基板适合用作载体。

公开(公告)号：US06469897B2

公开(公告)日：2002-10-22

申请号：US09774211

申请日：2001-01-30

申请人： Tzong-Da Ho ,  Chien-Ping Huang ,  Han-Ping Pu

发明人： Tzong-Da Ho ,  Chien-Ping Huang ,  Han-Ping Pu

IPC分类号： H05K720

CPC分类号： H01L23/49816 ,  H01L23/36 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  Y10T29/4935 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A TBGA (Tape Ball Grid Array) package assembly with grounded heat sink and method of fabricating the same is provided, which is constructed of a tape, a heat sink, and at least one semiconductor chip. The proposed TBGA technology is characterized by that a grounding plug is formed by first forming a via hole in the heat sink and a via hole in the tape without penetrating through the grounding solder-ball pad, and then filling an electrically-conductive material, such as solder or silver paste, into the heat-sink via hole from the top of the package assembly until filling up the tape via hole and the heat-sink via hole. As the semiconductor chip is mounted in position, its grounding pads are electrically bonded to the heat sink, thereby allowing the semiconductor chip to be externally grounded through the grounding plug, the grounding solder-ball pad, and the solder ball attached to the grounding solder-ball pad. The proposed TBGA technology allows the resulted grounding plug to be firmly secured in position due to the filled solder being wettable to the heat sink, thereby providing a greater ball shear strength to the grounding solder ball that is subsequently bonded to the grounding plug. The finished TBGA package would be therefore assured in the reliability of its grounding structure.

公开(公告)号：US06400036B1

公开(公告)日：2002-06-04

申请号：US09920069

申请日：2001-08-01

申请人： Wei-Sen Tang ,  Han-Ping Pu

发明人： Wei-Sen Tang ,  Han-Ping Pu

IPC分类号： H01L2144

CPC分类号： H01L24/32 ,  H01L21/563 ,  H01L24/28 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A flip-chip package technology is proposed for use to fabricate a dual-chip integrated circuit package that includes two semiconductor chips in a single package unit, which is characterized in the forming of a flash-barrier structure that can help prevent the underfill material used in flip-chip underfill process from flashing to other unintended areas. The flash-barrier structure can be either a protruded dam structure over the underlying semiconductor chip, or a groove in a coating layer formed over the underlying semiconductor chip. During flip-chip underfill process, the flash-barrier structure can confine the underfill material within the intended area and prevent the underfill material from flowing to other unintended areas such as nearby bonding pads, so that the finished package product can be assured in quality and reliability.

摘要翻译： 提出了一种倒装芯片封装技术，用于制造双芯片集成电路封装，其包括在单个封装单元中的两个半导体芯片，其特征在于形成闪光屏障结构，其可以帮助防止使用的底部填充材料 在从闪烁到其他非预期区域的倒装芯片底部填充过程中。 闪光屏障结构可以是下面的半导体芯片上的突出的坝结构，也可以是形成在下面的半导体芯片上的涂层中的凹槽。 在倒装芯片底部填充过程中，闪光屏障结构可以将底部填充材料限制在预期区域内，并防止底部填充材料流到其他非预期区域（例如附近的焊盘），从而可以确保成品包装产品的质量和 可靠性。

公开(公告)号：US09159686B2

公开(公告)日：2015-10-13

申请号：US13443556

申请日：2012-04-10

申请人： Yu-Feng Chen ,  Chun-Hung Lin ,  Han-Ping Pu ,  Chih-Hang Tung ,  Kai-Chiang Wu ,  Ming-Che Ho

发明人： Yu-Feng Chen ,  Chun-Hung Lin ,  Han-Ping Pu ,  Chih-Hang Tung ,  Kai-Chiang Wu ,  Ming-Che Ho

IPC分类号： H01L23/00 ,  H01L23/488

CPC分类号： H01L24/13 ,  H01L23/488 ,  H01L24/02 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05111 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10125 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13012 ,  H01L2224/13076 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor die includes a crack stopper on an under-bump metallization (UBM) layer. The crack stopper is in the shape of hollow cylinder with at least two openings.

摘要翻译： 半导体管芯包括在凸块下金属化（UBM）层上的裂纹阻挡层。 裂缝止动器为具有至少两个开口的中空圆筒形状。

公开(公告)号：US08970033B2

公开(公告)日：2015-03-03

申请号：US13035586

申请日：2011-02-25

申请人： Yu-Feng Chen ,  Yuh Chern Shieh ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Jiun Yi Wu ,  Tin-Hao Kuo

发明人： Yu-Feng Chen ,  Yuh Chern Shieh ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Jiun Yi Wu ,  Tin-Hao Kuo

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L24/16 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.

摘要翻译： 一种装置包括工件和工件表面上的金属迹线。 在工件的表面形成凸起跟踪（BOT）。 BOT结构包括金属凸块和将金属凸块接合到金属迹线的一部分的焊料凸块。 金属迹线包括未被焊料凸块覆盖的金属迹线延伸。

公开(公告)号：US08759964B2

公开(公告)日：2014-06-24

申请号：US11779192

申请日：2007-07-17

申请人： Han-Ping Pu ,  Mirng-Ji Lii

发明人： Han-Ping Pu ,  Mirng-Ji Lii

IPC分类号： H01L21/00

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/29099 ,  H01L2924/00

摘要： A method of forming a package structure with reduced damage to semiconductor dies is provided. The method includes providing a die comprising bond pads on a top surface of the die; forming bumps on the bond pads of the die, wherein the bumps have top surfaces higher than the top surface of the die; mounting the die on a chip carrier, wherein the bumps are attached to the chip carrier; molding the die onto the chip carrier with a molding compound; de-mounting the chip carrier from the die; and forming redistribution traces over, and electrically connected to, the bumps of the die.

摘要翻译： 提供一种形成具有对半导体管芯的损伤减小的封装结构的方法。 所述方法包括提供在所述管芯的顶表面上包括接合焊盘的管芯; 在所述模具的接合焊盘上形成凸起，其中所述凸起具有高于所述模具的顶表面的顶表面; 将所述管芯安装在芯片载体上，其中所述凸块附接到所述芯片载体上; 用模塑料将模具成型到芯片载体上; 将芯片载体从芯片上拆下; 以及在模具的凸起上形成并电连接到模具的凸块上的再分布迹线。

公开(公告)号：US20130119532A1

公开(公告)日：2013-05-16

申请号：US13294859

申请日：2011-11-11

申请人： Chun-Hung Lin ,  Yu-Feng Chen ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Hsien-Wei Chen

发明人： Chun-Hung Lin ,  Yu-Feng Chen ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Hsien-Wei Chen

IPC分类号： H01L23/485

CPC分类号： H01L24/14 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05024 ,  H01L2224/0508 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14179 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2224/05552

摘要： A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved.

摘要翻译： 芯片级半导体器件包括半导体管芯，第一突起和第二突起。 具有第一直径和第一高度的第一凸块形成在半导体管芯的外部区域上。 具有第二直径和第二高度的第二凸起形成在半导体管芯的内部区域上。 第二直径大于第一直径，而第二高度与第一高度相同。 通过改变凸块的形状，应力和应变可通过凸块重新分布。 结果，提高了芯片级半导体器件的热循环可靠性。

公开(公告)号：US07888236B2

公开(公告)日：2011-02-15

申请号：US11798432

申请日：2007-05-14

申请人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

发明人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11 ,  H01L2924/00014

摘要： A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings.

摘要翻译： 一种封装半导体器件的方法。 提供了包括分别由划线区域分隔的多个管芯的衬底，其中至少一层覆盖衬底。 通过光刻和蚀刻去除划线部分内的层的一部分以形成开口。 沿着划线区域锯切基板，通过开口。 在替代实施例中，提供了包括分别由第一划线区域分开的多个第一裸片的第一衬底，其中至少一个第一结构层覆盖在第一衬底上。 图案化第一结构层以在第一划线区域内形成第一开口。 提供了包括分别由第二划线区域分开的多个第二裸片的第二衬底，其中至少一个第二结构层覆盖在衬底上。 图案化第二结构层以在第二划线区域内形成第二开口。 第一基板和第二基板被接合以形成堆叠结构。 沿着第一和第二划线区域切割堆叠结构，使第一和第二开口通过。