公开(公告)号：US20040262028A1

公开(公告)日：2004-12-30

申请号：US10899515

申请日：2004-07-26

Inventor： Salvatore Bracaleone

IPC: H01B007/08

CPC classification number: H05K1/0245 ,  H01R12/523 ,  H01R13/622 ,  H01R13/746 ,  H01R24/44 ,  H01R24/542 ,  H01R24/56 ,  H01R25/003 ,  H01R2103/00 ,  H01R2107/00 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09636 ,  H05K2201/10356

Abstract: A Quadrax to Twinax conversion apparatus includes stacked trace layers of transmission line with a ground plane between the trace layers. Embodiments include trace layers of stripline or microstrip. Orthogonal plated through holes include a diagonal pair of through holes in electrical contact with traces on one of the trace layers and another diagonal pair of through holes in electrical contact with another trace layer. Contact pins extend through these orthogonal plated through holes with one pair of pins making electrical contact with one trace layer and the other pair of pins making electrical contact with another trace layer. The conversion apparatus electrically connects Twinax cables to respectively different trace layers without crossing over or disturbing the relative positions of the Quadrax diagonal pairs for very efficient high-speed data transfer from four wire Quadrax to two wire Twinax cables.

公开(公告)号：US06812803B2

公开(公告)日：2004-11-02

申请号：US10068622

申请日：2002-02-05

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H03H700

CPC classification number: H05K1/0245 ,  H05K1/0248 ,  H05K1/116 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4641 ,  H05K7/1459 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09718

Abstract: A high-speed router backplane, and method for its fabrication, are disclosed. The backplane uses differential signaling trace pairs on multiple high-speed signaling layers, the high-speed signaling layers separated by ground planes. Plated signaling thru-holes connect the trace pairs to the board surface for connection to external components. The signaling thru-holes pass through clearances in each ground plane. At selected ground planes, a conductive pad is patterned within each high-speed signaling thru-hole clearance, the pad slightly larger than the thru-hole diameter. The pads affect the impedance characteristics of the thru-holes, thus providing a better impedance match to the differential trace pairs, reducing signal reflections, and improving the ability to signal across the backplane at high speeds.

Abstract translation: 公开了一种高速路由器背板及其制造方法。 背板在多个高速信号层上使用差分信令跟踪对，高速信号层由接地层分开。 电镀信号通孔将走线对连接到电路板表面，以连接到外部组件。 信号通孔穿过每个接地平面内的间隙。 在选定的接地平面，每个高速信号通孔间隙内的导电焊盘都被图案化，焊盘略大于通孔直径。 这些焊盘影响通孔的阻抗特性，从而为差分走线对提供更好的阻抗匹配，减少信号反射，并提高高速信号跨背板的能力。

公开(公告)号：US20040039859A1

公开(公告)日：2004-02-26

申请号：US10224818

申请日：2002-08-21

Applicant: Intel Corporation

Inventor： Jiangqi He ,  Dong Zhong ,  David G. Figueroa ,  Yuan-Liang Li

IPC: G06F013/00

CPC classification number: H05K1/0245 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09718

Abstract: A circuit board including a conductive plane, a first via and a second via. The first and second vias extend through the conductive plane such that there is no conductive material between the first and second vias within the conductive plane.

Abstract translation: 一种电路板，包括导电平面，第一通孔和第二通孔。 第一和第二通孔延伸通过导电平面，使得在导电平面内的第一和第二通孔之间不存在导电材料。

公开(公告)号：US20030179049A1

公开(公告)日：2003-09-25

申请号：US10068622

申请日：2002-02-05

Applicant: Force10 Networks, Inc.

Inventor： Joel R. Goergen

IPC: H04B003/04

CPC classification number: H05K1/0245 ,  H05K1/0248 ,  H05K1/116 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4641 ,  H05K7/1459 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09718

Abstract: A high-speed router backplane, and method for its fabrication, are disclosed. The backplane uses differential signaling trace pairs on multiple high-speed signaling layers, the high-speed signaling layers separated by ground planes. Plated signaling thru-holes connect the trace pairs to the board surface for connection to external components. The signaling thru-holes pass through clearances in each ground plane. At selected ground planes, a conductive pad is patterned within each high-speed signaling thru-hole clearance, the pad slightly larger than the thru-hole diameter. The pads affect the impedance characteristics of the thru-holes, thus providing a better impedance match to the differential trace pairs, reducing signal reflections, and improving the ability to signal across the backplane at high speeds.

Abstract translation: 公开了一种高速路由器背板及其制造方法。 背板在多个高速信号层上使用差分信令跟踪对，高速信号层由接地层分开。 电镀信号通孔将走线对连接到电路板表面，以连接到外部组件。 信号通孔穿过每个接地平面内的间隙。 在选定的接地平面，每个高速信号通孔间隙内的导电焊盘都被图案化，焊盘略大于通孔直径。 这些焊盘影响通孔的阻抗特性，从而为差分走线对提供更好的阻抗匹配，减少信号反射，并提高高速信号跨背板的能力。

公开(公告)号：US20030177638A1

公开(公告)日：2003-09-25

申请号：US10068745

申请日：2002-02-05

Applicant: Force 10 Networks, Inc.

Inventor： Joel R. Goergen

IPC: H05K003/02 ,  H05K003/10

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.

Abstract translation: 所公开的板制造技术和设计特征使得能够构建用于路由器等的可靠的，高层次的和经济的背板，其需要以2.5Gbps或更高的速度跨越背板的大量信令路径，以及 作为路由器组件的大量功率分配。 所公开的技术和特征允许相对较厚（例如，三或四盎司铜）功率分配平面与公共背板中的大量高速信号层组合。 使用传统技术，由于需要的层数和配电层的厚度，这种结构将是不可能的。 所公开的实施例使用新颖的层布置，材料选择，处理技术和面板特征来在单个机械稳定的板中产生期望的高速层和低噪声大功率分配层。

公开(公告)号：US20020030266A1

公开(公告)日：2002-03-14

申请号：US09944218

申请日：2001-09-04

Applicant: Seiko Epson Corporation

Inventor： Akihiro Murata

IPC: H01L021/44 ,  H01L023/48

CPC classification number: H01L24/48 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H05K1/056 ,  H05K3/427 ,  H05K3/445 ,  H05K2201/0195 ,  H05K2201/09636 ,  H05K2201/09645 ,  H05K2203/1438 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/85399

Abstract: A semiconductor device comprising a substrate including a metal portion and a resin portion and having a plurality of through holes formed in the resin portion, conductive members formed within the through holes, a semiconductor chip attached to one surface of the substrate, and a plurality of solder balls attached to the other surface of the substrate. The semiconductor chip and solder balls are electrically connected through the conductive members.

Abstract translation: 一种半导体器件，包括：包括金属部分和树脂部分的基板，并且具有形成在所述树脂部分中的多个通孔，形成在所述通孔内的导电部件，附接到所述基板的一个表面的半导体芯片;以及多个 焊球附着在衬底的另一个表面上。 半导体芯片和焊球通过导电构件电连接。

公开(公告)号：US5541567A

公开(公告)日：1996-07-30

申请号：US323554

申请日：1994-10-17

Applicant: Keith E. Fogel ,  Jeffrey C. Hedrick ,  David A. Lewis ,  Eva E. Simonyi ,  Alfred Viehbeck ,  Stanley J. Whitehair

Inventor： Keith E. Fogel ,  Jeffrey C. Hedrick ,  David A. Lewis ,  Eva E. Simonyi ,  Alfred Viehbeck ,  Stanley J. Whitehair

IPC: H01F17/00 ,  H05K1/05 ,  H05K3/40 ,  H05K3/44 ,  H01F5/00 ,  H05K1/16

CPC classification number: H05K3/445 ,  H01F17/0006 ,  H05K1/056 ,  H05K2201/09636 ,  H05K2201/09881 ,  H05K2201/10416 ,  H05K3/4046

Abstract: Structures are described having vias with more than one electrical conductor at least one of which is a solid conductor which is formed by inserting the wire into the via in a substrate wherein the wire is attached to an electrically conductive plate which is spaced apart from the substrate by a spacer which leave a space between the substrate and plate. The space is filled with a dielectric material. The space with via between the conductor and via sidewall is filled with a dielectric material. The via is used for making transformers and inductors wherein one of the via conductors is used for inner windings and another of the via conductors is used for outer windings.

Abstract translation: 描述了具有多于一个电导体的通孔的结构，其中至少一个电导体是通过将电线插入基板中的通孔而形成的实心导体，其中导线附接到与基板间隔开的导电板 通过在基板和板之间留下空隙的间隔件。 该空间填充有电介质材料。 在导体和通孔侧壁之间具有通孔的空间填充有电介质材料。 通孔用于制造变压器和电感器，其中通孔导体之一用于内部绕组，另一个通孔导体用于外部绕组。

公开(公告)号：US20240321711A1

公开(公告)日：2024-09-26

申请号：US18606035

申请日：2024-03-15

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yingjiang Pu ,  Hang Jiang

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H05K1/0271 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09609 ,  H05K2201/09636

Abstract: A substrate includes a first dielectric layer having a first surface and a second surface. The first dielectric layer includes a plurality of first conductive vias and a plurality of second conductive vias. These two kinds of conductive vias are formed to penetrate the first dielectric layer and have different orientations for reduce warpage of the substrate.

公开(公告)号：US20240107661A1

公开(公告)日：2024-03-28

申请号：US18472051

申请日：2023-09-21

Applicant: KYOCERA Document Solutions Inc.

Inventor： Shotaro Ikegami

IPC: H05K1/02

CPC classification number: H05K1/0231 ,  H05K2201/09345 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/10159 ,  H05K2201/10651

Abstract: A signal processing board includes a six-layer substrate. A plurality of signal transmission planes are formed in a first layer, a third layer, a fourth layer, and a sixth layer. A first ground plane is formed in a second layer. A first power supply plane is formed in a fifth layer and electrically connected to the first semiconductor element. A second power supply plane is formed in the fifth layer and electrically connected to the second semiconductor element. A second ground plane is formed in the fifth layer. A first bypass capacitor is electrically connected to the first power supply plane and the second ground plane. A second bypass capacitor is electrically connected to the second power supply plane and the second ground plane.

公开(公告)号：US20240074055A1

公开(公告)日：2024-02-29

申请号：US17899477

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Walter L. Moden ,  Stephen F. Moxham ,  Travis M. Jensen

IPC: H05K1/11 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K1/116 ,  H01L21/4846 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H05K3/0014 ,  H05K3/0047 ,  H05K3/4038 ,  H01L24/16 ,  H05K2201/09563 ,  H05K2201/09636

Abstract: Substrates with continuous slot vias are disclosed herein. In one embodiment, a substrate comprises a first design layer, a second design layer, and an intermediary layer between the first and second design layers. The substrate further includes first and second signaling vias extending vertically through the intermediary layer between the first and second design layers. The first and second signaling vias route first and second data signals, respectively, between the first and second design layers. The substrate further includes a slot via that is positioned between the first and second signaling vias within the intermediary layer and extends laterally within the intermediary layer along a path that passes between the first signaling via and the second signaling via. The slot via can have a continuous shape such that the slot via shields the first and second data signals on the first and second signaling vias from crosstalk with one another.