公开(公告)号：US09797069B2

公开(公告)日：2017-10-24

申请号：US12534203

申请日：2009-08-03

申请人： Jer-Liang Andrew Yeh

发明人： Jer-Liang Andrew Yeh

IPC分类号： H01L23/00 ,  C30B33/10 ,  B82Y40/00 ,  H01L29/34 ,  H01L31/0236 ,  H01L29/06

CPC分类号： C30B33/10 ,  B82Y40/00 ,  H01L29/0665 ,  H01L29/34 ,  H01L31/02363 ,  Y02E10/50 ,  Y10T428/24355

摘要： The invention discloses a substrate with high fracture strength. The substrate according to the invention includes a plurality of nanostructures. The substrate has a first surface, and the nanostructures are protruded from the first surface. By the formation of the nanostructures, the fracture strength of the substrate is enhanced.

公开(公告)号：US09786763B2

公开(公告)日：2017-10-10

申请号：US15347157

申请日：2016-11-09

申请人： ROHM CO., LTD.

发明人： Kohei Shinsho

IPC分类号： H01L21/322 ,  H01L29/66 ,  H01L21/324 ,  H01L29/10 ,  H01L29/34 ,  H01L29/36 ,  H01L29/739 ,  H01L29/732

CPC分类号： H01L29/66333 ,  H01L21/268 ,  H01L21/324 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/34 ,  H01L29/36 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397

摘要： A method of manufacturing a semiconductor device includes: forming a lattice defect layer in a substrate having a front surface region where a bipolar element of a pn junction type is formed and a rear surface region opposing the front surface region, the lattice defect layer being formed by injecting a charged particle to a first region in the rear surface region of the substrate; forming a laminated region, in which a first conductivity type impurity region and a second conductivity type impurity region are sequentially laminated from a rear surface side of the substrate toward the first region, in a second region in the rear surface region of the substrate, the first region being positioned deeper than the second region from a rear surface of the substrate; and selectively activating the laminated region by laser annealing after the formation of the laminated region and the lattice defect layer.

公开(公告)号：US20170148639A1

公开(公告)日：2017-05-25

申请号：US15351289

申请日：2016-11-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun Hsiung Tsai ,  Tsz-Mei Kwok

IPC分类号： H01L21/311 ,  H01L21/02 ,  H01L29/08 ,  H01L29/34

CPC分类号： H01L21/31111 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02664 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/34 ,  H01L29/36 ,  H01L29/41783

摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In an embodiment, a method of manufacturing a semiconductor device may include providing a substrate having a recess; epitaxially forming a first layer including a doped semiconductor material within the recess; and epitaxially forming a second layer including an undoped semiconductor material over at least a portion of the recess.

公开(公告)号：US20170125418A1

公开(公告)日：2017-05-04

申请号：US15407598

申请日：2017-01-17

申请人： Samsung Electronics Co., Ltd.

发明人： JAEYOUNG PARK ,  SUNGHO KANG ,  KICHUL KIM ,  Sunyoung LEE ,  HAN KI LEE ,  BONYOUNG KOO

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L29/34 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/0206 ,  H01L21/302 ,  H01L21/306 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/34 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

摘要： A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700° C.

公开(公告)号：US20170098701A1

公开(公告)日：2017-04-06

申请号：US15240745

申请日：2016-08-18

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Hidemoto TOMITA ,  Masakazu KANECHIKA ,  Hiroyuki UEDA

IPC分类号： H01L29/778 ,  H01L29/34 ,  H01L29/47 ,  H01L29/20 ,  H01L29/205

CPC分类号： H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/34 ,  H01L29/432 ,  H01L29/475 ,  H01L29/7786

摘要： A semiconductor device includes: an electron transit layer constituted of GaN; an electron supply layer constituted of Inx1Aly1Ga1-x1-y1N (0≦x1

公开(公告)号：US09576840B2

公开(公告)日：2017-02-21

申请号：US14543820

申请日：2014-11-17

申请人： Samsung Electronics Co., Ltd.

发明人： Jaeyoung Park ,  Sungho Kang ,  Kichul Kim ,  Sunyoung Lee ,  Han Ki Lee ,  Bonyoung Koo

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/762 ,  H01L29/66 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/0206 ,  H01L21/302 ,  H01L21/306 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/34 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

摘要： A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700.

摘要翻译： 一种制造半导体器件的方法包括在衬底中形成第一多个凹陷区域，所述衬底在所述第一多个凹陷区域之间具有突出的有源区域和所述突出的有源区域具有上表面和侧壁，形成器件隔离 在所述第一多个凹陷区域中的膜，所述器件隔离膜暴露所述突出的有源区的所述上表面和所述侧壁的上部，并且对所述突出的有源区的所述暴露表面进行第一等离子体处理，其中所述等离子体处理 使用包含惰性气体和氢气中的至少一种的等离子体气体在小于或等于约700℃的温度下进行。

公开(公告)号：US20160359006A1

公开(公告)日：2016-12-08

申请号：US15221500

申请日：2016-07-27

申请人： Synopsys, Inc.

发明人： Tsu-Jae King Liu ,  Victor Moroz

IPC分类号： H01L29/34 ,  H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L23/544 ,  H01L21/78 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/34 ,  H01L21/78 ,  H01L21/84 ,  H01L23/544 ,  H01L27/0886 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785 ,  H01L2223/5446 ,  Y10S438/974

摘要： By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

摘要翻译： 通过在具有预先存在的半导体材料的脊（即，“波纹状基板”）的基板上形成MOSFET，可以克服与常规半导体制造工艺相关的分辨率限制，并且可以可靠地实现高性能的低功率晶体管， 重复生产。 在实际的器件形成之前形成波纹状衬底可以使用通常不适于器件生产的高精度技术来产生波纹衬底上的脊。 随后将高精度脊结合到其沟道区中的MOSFET通常将显示出比使用不能提供相同程度的图案精度的基于光刻技术形成的类似的MOSFET更精确和更少可变的性能。 附加的性能增强技术，例如脉冲形掺杂和“包裹”栅极可以与分段通道区域一起使用，以进一步提高器件性能。

公开(公告)号：US09478611B2

公开(公告)日：2016-10-25

申请号：US14715041

申请日：2015-05-18

申请人： IMEC VZW

发明人： Boon Teik Chan ,  Clement Merckling

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786 ,  H01L29/04 ,  H01L29/20 ,  H01L29/34 ,  H01L21/02 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/41

CPC分类号： H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02538 ,  H01L21/02603 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/20 ,  H01L29/34 ,  H01L29/413 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78642 ,  H01L29/78681

摘要： An example semiconductor structure comprises a first surface and at least one nanowire, the at least one nanowire being perpendicular to the first surface, wherein the first surface is defect-poor and is made of a doped III-V semiconductor material, wherein the at least one nanowire is defect-poor and made of an undoped III-V semiconductor material having a lattice mismatch with the material of the first surface of from about 0% to 1%.

摘要翻译： 示例性半导体结构包括第一表面和至少一个纳米线，所述至少一个纳米线垂直于所述第一表面，其中所述第一表面是缺陷差的并且由掺杂的III-V半导体材料制成，其中所述至少一个 一个纳米线是缺陷缺陷的，并且由与第一表面的材料具有约0％至1％的晶格失配的未掺杂的III-V半导体材料制成。

公开(公告)号：US20160265139A1

公开(公告)日：2016-09-15

申请号：US15162115

申请日：2016-05-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ji-Soo Park

IPC分类号： C30B25/18 ,  C30B29/08 ,  H01L29/34 ,  H01L21/02 ,  H01L29/165 ,  C30B29/40 ,  H01L29/06

CPC分类号： C30B25/186 ,  C30B25/04 ,  C30B29/08 ,  C30B29/40 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02518 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/0684 ,  H01L29/165 ,  H01L29/34

摘要： A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.

摘要翻译： 一种器件包括在由绝缘体限制的区域内的外延生长的晶体材料。 结晶材料的表面具有减小的粗糙度。 一个实例包括通过产生导致晶体的主要生长成分从绝缘体的侧壁横向供应的工艺参数来获得具有减小的粗糙度的表面。 在优选实施例中，由绝缘体限制的区域是具有足以使用ART技术捕获缺陷的纵横比的绝缘体中的开口。

公开(公告)号：US09343535B2

公开(公告)日：2016-05-17

申请号：US14019638

申请日：2013-09-06

申请人： Jung-Do Lee ,  Tae-Woo Kang ,  Dong-Han Kim ,  Jang-Woo Lee

发明人： Jung-Do Lee ,  Tae-Woo Kang ,  Dong-Han Kim ,  Yang-Hoon Ahn ,  Jang-Woo Lee ,  Dae-Young Choi

IPC分类号： H01L23/34 ,  H01L29/34 ,  H01L29/10 ,  H01L23/367 ,  H01L23/00 ,  H01L23/42 ,  H01L23/433 ,  H01L21/56 ,  H01L25/10 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L29/34 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/49811 ,  H01L24/97 ,  H01L25/105 ,  H01L29/1033 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/10271 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package includes a first package board, a first semiconductor chip arranged on the first package board, a heat transfer layer arranged on the first semiconductor chip, a heat spreader arranged on the heat transfer layer, and a housing having a molding part arranged on the first package board and directly surrounding side surfaces of the first semiconductor chip and a guide wall arranged on the molding part, with the guide wall spaced apart from the heat spreader and surrounding side surfaces of the heat spreader.

摘要翻译： 一种半导体封装，包括第一封装板，布置在第一封装板上的第一半导体芯片，布置在第一半导体芯片上的传热层，布置在传热层上的散热器，以及具有布置在 所述第一封装板和所述第一半导体芯片的直接环绕的侧表面和布置在所述模制部件上的引导壁，所述引导壁与所述散热器间隔开并且所述散热器的周围侧表面。