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    N-FET with a Highly Doped Source/Drain and Strain Booster
    84.
    发明申请
    N-FET with a Highly Doped Source/Drain and Strain Booster 有权
    具有高掺杂源/漏极和应变增强器的N-FET

    公开(公告)号：US20100155790A1

    公开(公告)日：2010-06-24

    申请号：US12341674

    申请日：2008-12-22

    Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

    Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L21/28255 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/7833

    Abstract: A structure and method of making an N-FET with a highly doped source/drain and strain booster are presented. The method provides a substrate with a Ge channel region. A gate dielectric is formed over the Ge channel and a gate electrode is formed over the gate dielectric. Sacrificial gate spacers are disposed on the sidewalls of the gate dielectric and gate electrode. Cavities are etched into the substrate extending under the sacrificial gate spacers. Si1−xGex source/drain regions are doped in-situ during formation, x

    Abstract translation: 提出了制造具有高掺杂源/漏和应变增强器的N-FET的结构和方法。 该方法提供具有Ge沟道区的衬底。 在Ge沟道上方形成栅极电介质，在栅极电介质上形成栅电极。 牺牲栅间隔件设置在栅极电介质和栅电极的侧壁上。 凹坑被蚀刻到在牺牲栅极间隔物下面延伸的衬底中。 Si1-xGex源/漏区在形成期间原位掺杂，x <0.85。

    Method to solve via poisoning for porous low-k dielectric
    85.
    发明授权
    Method to solve via poisoning for porous low-k dielectric 有权
    解决多孔低介电常数中毒的方法

    公开(公告)号：US07250683B2

    公开(公告)日：2007-07-31

    申请号：US11056758

    申请日：2005-02-11

    Applicant: Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

    Inventor： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

    Abstract: A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

    Abstract translation: 公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。 通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。 在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。 所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

    Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process
    86.
    发明授权
    Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process 有权
    在铜镶嵌工艺中制造对低k电介质层的屏障粘附的方法

    公开(公告)号：US06342448B1

    公开(公告)日：2002-01-29

    申请号：US09583401

    申请日：2000-05-31

    Applicant: Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

    Inventor： Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC: H01L2144

    CPC classification number: H01L21/76846 ,  H01L21/28568 ,  H01L21/76807 ,  H01L21/76873

    Abstract: A method for forming an improved TaN copper barrier for a copper damascene process is described which has improved adhesion to low-k dielectric layers and also improves the wetting of a copper seed layer deposited over it thereby improving the structure of the copper seed layer which is critical to achieving uniform, high quality electrochemical copper deposition. The copper barrier is a composite structure having an lower thin Ta rich TaN portion which mixes into and reacts with the surface of the low-k dielectric layer, forming a strongly bonded transition layer between the low-k material and the remaining portion of the barrier layer. The presence of the transition layer causes compressive film stress rather than tensile stress as found in the conventional TaN barrier. As a result, the barrier layer does not delaminate from the low-k layer during subsequent processing. A second thick central portion of the barrier layer is formed of stoichiometric TaN which benefits subsequent CMP of the copper damascene structure. An upper thin Ta portion improves barrier wetting to the copper seed layer. The three sections of the laminar barrier are sequentially deposited in a single pumpdown operation by IMP sputtering from a Ta target.

    Abstract translation: 描述了一种用于形成用于铜镶嵌工艺的改进的TaN铜阻挡层的方法，其具有改善的对低k电介质层的粘附性，并且还改善了沉积在其上的铜籽晶层的润湿，从而改善了铜籽晶层的结构， 对于实现均匀，高质量的电化学铜沉积至关重要。 铜屏障是具有较低的Ta Ta薄部分的复合结构，其混合并与低k电介质层的表面反应，在低k材料与阻挡层的剩余部分之间形成牢固结合的过渡层 层。 过渡层的存在导致压缩膜应力而不是常规TaN阻挡层中的拉伸应力。 结果，在随后的处理期间，阻挡层不会从低k层分层。 阻挡层的第二厚中心部分由化学计量的TaN形成，这有利于铜镶嵌结构的后续CMP。 上部薄的Ta部分改善了对铜种子层的屏障润湿。 层状阻挡层的三个部分通过来自Ta靶的IMP溅射在单次抽运操作中依次沉积。

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