公开(公告)号：US20170287857A1

公开(公告)日：2017-10-05

申请号：US15624493

申请日：2017-06-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Satish Yeldandi

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/038 ,  H01L2224/0382 ,  H01L2224/039 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05583 ,  H01L2224/05584 ,  H01L2224/05687 ,  H01L2224/94 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/365 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/054 ,  H01L2224/03

Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

公开(公告)号：US20160351530A1

公开(公告)日：2016-12-01

申请号：US15232525

申请日：2016-08-09

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Luke G. England ,  Owen R. Fay

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/11822 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14134 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/16505 ,  H01L2224/1701 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29316 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29499 ,  H01L2224/3201 ,  H01L2224/32054 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/3301 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81125 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81901 ,  H01L2224/81948 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/07811 ,  H01L2924/1461 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00012

Abstract: Semiconductor devices and device packages include at least one semiconductor die electrically coupled to a substrate through a plurality of conductive structures. The at least one semiconductor die may be a plurality of memory dice, and the substrate may be a logic die. An underfill material disposed between the at least one semiconductor die and the substrate may include a thermally conductive material. An electrically insulating material is disposed between the plurality of conductive structures and the underfill material. Methods of attaching a semiconductor die to a substrate, such as for forming semiconductor device packages, include covering or coating at least an outer side surface of conductive structures, electrically coupling the semiconductor die to the substrate with an electrically insulating material, and disposing a thermally conductive material between the semiconductor die and the substrate.

Abstract translation: 半导体器件和器件封装包括通过多个导电结构电耦合到衬底的至少一个半导体管芯。 所述至少一个半导体管芯可以是多个存储器管芯，并且所述衬底可以是逻辑管芯。 设置在至少一个半导体管芯和衬底之间的底部填充材料可以包括导热材料。 电绝缘材料设置在多个导电结构和底部填充材料之间。 将半导体管芯附着到诸如用于形成半导体器件封装的衬底的方法包括覆盖或涂覆导电结构的至少外侧表面，用电绝缘材料将半导体管芯电耦合到衬底，并且设置热 导电材料在半导体管芯和衬底之间。

公开(公告)号：US20160013173A1

公开(公告)日：2016-01-14

申请号：US14330805

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/3675 ,  H01L23/44 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/156 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Abstract translation: 封装半导体管芯组件的方法。 在一个实施例中，一种方法涉及将具有第一管芯和多个第二管芯的半导体管芯组件封装在第一管芯上，其中第一管芯具有从第二管芯的堆叠体横向向外延伸的周边区域 。 该方法可以包括将热传递结构耦合到第一模具的周边区域并且在第二模具之间流动底部填充材料。 在将热传递结构连接到第一模具的周边区域之后，底部填充材料流动，使得热转印结构限制底部填充材料的横向流动。

公开(公告)号：US20150206813A1

公开(公告)日：2015-07-23

申请号：US14162537

申请日：2014-01-23

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L23/06 ,  H01L23/18 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/50 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/50 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/3675 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68386 ,  H01L2225/1017 ,  H01L2225/1041 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of processing a semiconductor device include attaching a semiconductor substrate to a carrier substrate, forming a silane material over an exposed portion of the carrier substrate, and curing the silane material to form a hydrophobic coating over the carrier substrate. The hydrophobic coating may reduce or prevent undercut of the semiconductor substrate due to wicking of adhesive from between the semiconductor substrate and the carrier substrate during processing. The silane material includes a compound having a chemical formula of (XO)3Si(CH2)nY, (XO)2Si((CH2)nY)2, or (XO)3Si(CH2)nY(CH2)nSi(XO)3, wherein XO is a hydrolyzable alkoxy group, Y is an organofunctional group, and n is a nonnegative integer. Some methods include forming a silane material over an exposed portion of a substrate, attaching a semiconductor device stack over the substrate, and forming an underfill material between substrates of the semiconductor device stack. Related structures are also disclosed.

Abstract translation: 处理半导体器件的方法包括将半导体衬底附接到载体衬底，在载体衬底的暴露部分上形成硅烷材料，并固化硅烷材料以在载体衬底上形成疏水涂层。 疏水涂层可以在处理期间由于半导体衬底和载体衬底之间的粘合剂的芯吸而减少或防止半导体衬底的底切。 硅烷材料包括具有化学式为（XO）3 Si（CH 2）n Y，（XO）2 Si（（CH 2）n Y）2或（XO）3 Si（CH 2）n Y（CH 2）n Si（XO） 其中XO是可水解的烷氧基，Y是有机官能团，n是非负整数。 一些方法包括在衬底的暴露部分上形成硅烷材料，将半导体器件堆叠附着在衬底上，以及在半导体器件堆叠的衬底之间形成底部填充材料。 还公开了相关结构。

公开(公告)号：US20150162302A1

公开(公告)日：2015-06-11

申请号：US14625325

申请日：2015-02-18

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/06181 ,  H01L2224/10145 ,  H01L2224/1182 ,  H01L2224/11824 ,  H01L2224/11848 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81355 ,  H01L2224/81815 ,  H01L2224/81911 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/3651 ,  H01L2924/00012 ,  H01L2924/01016 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Semiconductor assemblies, structures, and methods of fabrication are disclosed. A coating is formed on an electrically conductive pillar. The coating, which may be formed from at least one of a silane material and an organic solderability protectant material, may bond to a conductive material of the electrically conductive pillar and, optionally, to other metallic materials of the electrically conductive pillar. The coating may also bond to substrate passivation material, if present, or to otherwise-exposed surfaces of a substrate and a bond pad. The coating may be selectively formed on the conductive material. Material may not be removed from the coating after formation thereof and before reflow of the solder for die attach. The coating may isolate at least the conductive material from solder, inhibiting solder wicking or slumping along the conductive material and may enhance adhesion between the resulting bonded conductive element and an underfill material.

Abstract translation: 公开了半导体组件，结构和制造方法。 在导电柱上形成涂层。 可以由硅烷材料和有机可焊性保护剂材料中的至少一种形成的涂层可以结合到导电柱的导电材料和任选地粘合到导电柱的其它金属材料。 涂层还可以结合到基底钝化材料（如果存在）上，或者粘合到基底和接合垫的其它暴露表面。 可以在导电材料上选择性地形成涂层。 在其形成之后并且在用于管芯附着的焊料的回流之前，材料可能不会从涂层中去除。 涂层可以至少将导电材料与焊料隔离开来，阻止焊料芯吸或沿导电材料塌陷，并且可以增强所得到的粘合的导电元件和底部填充材料之间的粘附。

公开(公告)号：US08962449B1

公开(公告)日：2015-02-24

申请号：US13954133

申请日：2013-07-30

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L21/22 ,  H01L21/38 ,  H01L21/762 ,  H01L29/02

CPC classification number: H01L24/50 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/78 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2924/12042 ,  H01L2924/00012

Abstract: Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at least adjacent a periphery of the carrier substrate, adhesively bonding another substrate to the carrier substrate, and separating the another substrate from the carrier substrate. The silane material includes a compound having a structure of (XO)3Si(CH2)nY, (XO)2Si((CH2)nY)2, or (XO)3Si(CH2)nY(CH2)nSi(XO)3, wherein XO is a hydrolyzable alkoxy group, Y is an organofunctional group, and n is a nonnegative integer. Some methods include forming a polymeric material comprising Si—O—Si over a first substrate, removing a portion of the polymeric material, and adhesively bonding another substrate to the first substrate. Structures include a polymeric material comprising Si—O—Si disposed over a first substrate, an adhesive material disposed over the first substrate and at least a portion of the polymeric material, and a second substrate disposed over the adhesive material.

Abstract translation: 形成半导体结构的方法包括将载体衬底暴露于硅烷材料以形成涂层，至少邻近载体衬底的周边移除涂层的一部分，将另一衬底粘合到载体衬底上，并分离另一衬底 从载体衬底。 硅烷材料包括具有（XO）3 Si（CH 2）n Y，（XO）2 Si（（CH 2）n Y）2或（XO）3 Si（CH 2）n Y（CH 2）n Si（XO）3的结构的化合物，其中 XO是可水解的烷氧基，Y是有机官能团，n是非负整数。 一些方法包括在第一衬底上形成包含Si-O-Si的聚合材料，去除聚合物材料的一部分，并将另一衬底粘合到第一衬底上。 结构包括设置在第一衬底上的Si-O-Si的聚合物材料，设置在第一衬底上的粘合剂材料和聚合物材料的至少一部分，以及设置在粘合剂材料上的第二衬底。

公开(公告)号：US20150035126A1

公开(公告)日：2015-02-05

申请号：US13954133

申请日：2013-07-30

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L21/762 ,  H01L29/02

CPC classification number: H01L24/50 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/78 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2924/12042 ,  H01L2924/00012

Abstract: Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at least adjacent a periphery of the carrier substrate, adhesively bonding another substrate to the carrier substrate, and separating the another substrate from the carrier substrate. The silane material includes a compound having a structure of (XO)3Si(CH2)nY, (XO)2Si((CH2)nY)2, or (XO)3Si(CH2)nY(CH2)nSi(XO)3, wherein XO is a hydrolyzable alkoxy group, Y is an organofunctional group, and n is a nonnegative integer. Some methods include forming a polymeric material comprising Si—O—Si over a first substrate, removing a portion of the polymeric material, and adhesively bonding another substrate to the first substrate. Structures include a polymeric material comprising Si—O—Si disposed over a first substrate, an adhesive material disposed over the first substrate and at least a portion of the polymeric material, and a second substrate disposed over the adhesive material.

Abstract translation: 形成半导体结构的方法包括将载体衬底暴露于硅烷材料以形成涂层，至少邻近载体衬底的周边移除涂层的一部分，将另一衬底粘合到载体衬底上，并分离另一衬底 从载体衬底。 硅烷材料包括具有（XO）3 Si（CH 2）n Y，（XO）2 Si（（CH 2）n Y）2或（XO）3 Si（CH 2）n Y（CH 2）n Si（XO）3的结构的化合物，其中 XO是可水解的烷氧基，Y是有机官能团，n是非负整数。 一些方法包括在第一衬底上形成包含Si-O-Si的聚合材料，去除聚合物材料的一部分，并将另一衬底粘合到第一衬底上。 结构包括设置在第一衬底上的Si-O-Si的聚合物材料，设置在第一衬底上的粘合剂材料和聚合物材料的至少一部分，以及设置在粘合剂材料上的第二衬底。

公开(公告)号：US20140291834A1

公开(公告)日：2014-10-02

申请号：US13851788

申请日：2013-03-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  Luke G. England ,  Owen R. Fay

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/11822 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14134 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/16505 ,  H01L2224/1701 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29316 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29499 ,  H01L2224/3201 ,  H01L2224/32054 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/3301 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81125 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81901 ,  H01L2224/81948 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/07811 ,  H01L2924/1461 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00012

Abstract: Semiconductor devices and device packages include at least one semiconductor die electrically coupled to a substrate through a plurality of conductive structures. The at least one semiconductor die may be a plurality of memory dice, and the substrate may be a logic die. An underfill material disposed between the at least one semiconductor die and the substrate may include a thermally conductive material. An electrically insulating material is disposed between the plurality of conductive structures and the underfill material. Methods of attaching a semiconductor die to a substrate, such as for forming semiconductor device packages, include covering or coating at least an outer side surface of conductive structures, electrically coupling the semiconductor die to the substrate with an electrically insulating material, and disposing a thermally conductive material between the semiconductor die and the substrate.

Abstract translation: 半导体器件和器件封装包括通过多个导电结构电耦合到衬底的至少一个半导体管芯。 所述至少一个半导体管芯可以是多个存储器管芯，并且所述衬底可以是逻辑管芯。 设置在至少一个半导体管芯和衬底之间的底部填充材料可以包括导热材料。 电绝缘材料设置在多个导电结构和底部填充材料之间。 将半导体管芯附着到诸如用于形成半导体器件封装的衬底的方法包括覆盖或涂覆导电结构的至少外侧表面，用电绝缘材料将半导体管芯电耦合到衬底，并且设置热 导电材料在半导体管芯和衬底之间。

公开(公告)号：US20140159239A1

公开(公告)日：2014-06-12

申请号：US13712699

申请日：2012-12-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mark A. Bossler ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Randall S. Parker

IPC: H01L23/538 ,  H01L21/306

CPC classification number: H01L23/53238 ,  H01L21/02068 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.

Abstract translation: 一种用于从衬底选择性地去除材料的方法，而不损害填充通孔的铜，并且至少部分地延伸通过衬底。 该方法包括氧化包括基底和至少一个铜特征的半导体结构，并且使用包含SF 6的蚀刻剂去除一部分基底，而不在至少一个铜特征上形成硫化铜。 还公开了另外的方法，以及由这些方法制备的半导体结构。

公开(公告)号：US20130240939A1

公开(公告)日：2013-09-19

申请号：US13870740

申请日：2013-04-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  Tongbi Jiang

IPC: H01L33/10

CPC classification number: H01L33/10 ,  H01L33/0079 ,  H01L33/0095 ,  H01L33/46

Abstract: Solid state lighting devices having side reflectivity and associated methods of manufacturing are disclosed herein. In one embodiment, a method of forming a solid state lighting device includes attaching a solid state emitter to a support substrate, mounting the solid state emitter and support substrate to a temporary carrier, and cutting kerfs through the solid state emitter and the substrate to separate individual dies. The solid state emitter can have a first semiconductor material, a second semiconductor material, and an active region between the first and second semiconductor materials. The individual dies can have sidewalls that expose the first semiconductor material, active region and second semiconductor material. The method can further include applying a reflective material into the kerfs and along the sidewalls of the individual dies.

Abstract translation: 本文公开了具有侧反射率和相关制造方法的固态照明装置。 在一个实施例中，形成固态照明装置的方法包括将固态发射器附接到支撑衬底，将固态发射器和支撑衬底安装到临时载体上，以及通过固态发射器和衬底切割缝隙以分离 个人死亡 固态发射器可以具有第一半导体材料，第二半导体材料和第一和第二半导体材料之间的有源区。 各个管芯可以具有露出第一半导体材料，有源区和第二半导体材料的侧壁。 该方法还可以包括将反射材料施加到切口中并且沿着各个模具的侧壁。