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    Multi-layer circuit substrates and electrical assemblies having conductive composition connectors
    6.
    发明授权
    Multi-layer circuit substrates and electrical assemblies having conductive composition connectors 有权
    具有导电组合物连接器的多层电路基板和电气组件

    公开(公告)号：US6054761A

    公开(公告)日：2000-04-25

    申请号：US203126

    申请日：1998-12-01

    申请人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Solomon I. Beilin ,  Albert Wong Chan ,  Yasuhito Takahashi

    发明人： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Solomon I. Beilin ,  Albert Wong Chan ,  Yasuhito Takahashi

    IPC分类号： C08K3/00 ,  C08L63/00 ,  H01L23/498 ,  H05K3/40 ,  H05K3/46 ,  H01L23/04

    CPC分类号： H05K3/363 ,  H01L23/49883 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H01L2224/16503 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10666 ,  H05K2203/0425 ,  H05K2203/0455 ,  H05K3/321 ,  H05K3/4623

    摘要： Printed circuit substrates and electrical assemblies including a conductive composition are disclosed. The printed circuit substrate and the electrical assembly embodiments comprise a first conducting region and a second conducting region. A dielectric layer is disposed between the first and second conducting regions. An aperture is disposed in the dielectric layer and a via structure including the conductive composition is disposed in the aperture. The conductive composition is preferably in a cured state and electrically communicates with the first and second conducting regions. In preferred embodiments, the conductive composition comprises conductive particles in an amount of at least about 75 wt. % based on the weight of the composition. At least 50% by weight of the conductive particles have melting points of less than about 400.degree. C. The composition further includes a carrier including an epoxy-functional resin in an amount of at least about 50 wt. % based on the weight of the carrier, and a fluxing agent in an amount of at least about 0.1 wt % based on the weight of the carrier. The epoxy functional resin can have a viscosity of less than about 1000 centipoise at 25.degree. C.

    摘要翻译： 公开了印刷电路基板和包括导电组合物的电气组件。 印刷电路基板和电组件实施例包括第一导电区域和第二导电区域。 电介质层设置在第一和第二导电区域之间。 在电介质层中设置孔，并且包括导电组合物的通孔结构设置在孔中。 导电组合物优选处于固化状态并与第一和第二导电区域电连通。 在优选的实施方案中，导电组合物包含至少约75wt。 基于组合物的重量％。 至少50重量％的导电颗粒具有小于约400℃的熔点。该组合物还包括载体，其包含至少约50重量％的量的环氧官能树脂。 基于载体的重量，以及基于载体重量的至少约0.1重量％的助熔剂。 环氧官能树脂在25℃下的粘度可以小于约1000厘泊

    Methods of planarizing structures on wafers and substrates by polishing
    9.
    发明授权
    Methods of planarizing structures on wafers and substrates by polishing 失效
    通过抛光对晶片和基板上的结构进行平面化的方法

    公开(公告)号：US06733685B2

    公开(公告)日：2004-05-11

    申请号：US09881514

    申请日：2001-06-12

    申请人： Solomon I. Beilin ,  Michael G. Lee ,  William T. Chou ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

    发明人： Solomon I. Beilin ,  Michael G. Lee ,  William T. Chou ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

    IPC分类号： B44C122

    CPC分类号： H01L21/31053 ,  H05K3/243 ,  H05K3/4647 ,  H05K2203/025 ,  H05K2203/0733

    摘要： Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

    摘要翻译： 公开了在基板和晶片的表面上形成的结构的平面化方法。 所述方法在所述表面和所述结构或所述结构将被形成的位置上形成平坦化层，使得所述层的顶表面在所述结构的位置之间具有低区域，并且使得所述低区域基本上位于 在低于结构顶部的平面内。 在平坦化层的低面积上形成抛光停止层，抛光停止层比平坦化层更能抵抗抛光，优选结构。 然后将所得表面抛光。 抛光可以通过例如标准机械抛光和化学机械抛光来实现。

    Fabrication procedure for a stable post
    10.
    发明授权
    Fabrication procedure for a stable post 失效
    一个稳定的岗位的制作程序

    公开(公告)号：US5722162A

    公开(公告)日：1998-03-03

    申请号：US541219

    申请日：1995-10-12

    申请人： William T. Chou ,  Solomon I. Beilin ,  David A. Horine ,  David Kudzuma ,  Michael G. Lee ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

    发明人： William T. Chou ,  Solomon I. Beilin ,  David A. Horine ,  David Kudzuma ,  Michael G. Lee ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

    IPC分类号： G03F7/26 ,  H01L21/48 ,  H01L23/12 ,  H01L23/52 ,  H05K3/18 ,  H05K3/40 ,  H05K3/10

    CPC分类号： H05K3/4007 ,  H01L21/4853 ,  H01L2924/00013 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2203/0577 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204

    摘要： An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.

    摘要翻译： 通过在基板上形成第一层正性光致抗蚀剂，通过在第一层上软化烘烤该第一层并将其暴露在短时间内，用一个整体电路芯片来形成用于安装诸如集成电路芯片的微电子器件的互连柱， 宽孔径面罩或简单的UV空白洪水曝光。 在不显影第一层的情况下，将第二层正性抗蚀剂涂覆在第一层上，软化，然后用窄孔径掩模曝光。 在第二层的软烘烤期间，光致抗蚀剂化合物中的一些活化剂扩散到第一层的暴露部分，并以这样的方式改变其溶解度，使得当这些层随后显影时，显影剂部分地削弱未曝光 第一层的部分以在光致抗蚀剂中形成具有大致均匀横截面的开口。 然后可以通过电镀填充该开口以产生强大的整体互连柱。