摘要:
An optical apparatus including an optical substrate having an embedded waveguide and an optical device adapted to receive light transmitted from an end of the waveguide. The optical apparatus includes a coupling structure for coupling the optical device to the substrate. The coupling structure has a thin metallic layer with an aperture. At least a portion of the optical device is disposed in the aperture. A method for making an optical apparatus comprising forming an optical substrate having a waveguide embedded therein; depositing a metal layer over an end of the waveguide; and depositing a polymeric layer over the metal layer. An aperture is formed in the metal layer and in the polymeric layer by removing a portion of the metal layer and a portion of the polymeric layer disposed over the end of the waveguide. The method for making an optical apparatus also comprises inserting at least a portion of an optical device within the aperture so that the optical device is positioned to receive light from the first end of the waveguide.
摘要:
An optoreflective structure for reflecting an optical signal following a path defined by an optical waveguide comprising a first cladding layer having a first planar cladding surface; a waveguide disposed on the first cladding layer; and a second cladding layer disposed on the waveguide and having a second planar cladding surface. The first cladding layer, the second cladding layer and the waveguide terminate in a generally dove-tailed structure having a beveled planar surface. An optoreflector is disposed on the beveled planar surface for a changing direction of an optical signal passing through the waveguide. Methods of producing the optoreflective structure are disclosed.
摘要:
Printed circuit substrates and electrical assemblies including a conductive composition are disclosed. The printed circuit substrate and the electrical assembly embodiments comprise a first conducting region and a second conducting region. A dielectric layer is disposed between the first and second conducting regions. An aperture is disposed in the dielectric layer and a via structure including the conductive composition is disposed in the aperture. The conductive composition is preferably in a cured state and electrically communicates with the first and second conducting regions. In preferred embodiments, the conductive composition comprises conductive particles in an amount of at least about 75 wt. % based on the weight of the composition. At least 50% by weight of the conductive particles have melting points of less than about 400.degree. C. The composition further includes a carrier including an epoxy-functional resin in an amount of at least about 50 wt. % based on the weight of the carrier, and a fluxing agent in an amount of at least about 0.1 wt % based on the weight of the carrier. The epoxy functional resin can have a viscosity of less than about 1000 centipoise at 25.degree. C.
摘要:
Methods for making circuit substrates and electrical assemblies are disclosed. A conductive composition is disposed between confronting conductive regions and can be cured to form a via structure. The conductive composition includes conductive particles and a carrier. The carrier can include a fluxing agent and an epoxy-functional resin having a viscosity of less than about 1000 centipoise at 25° C.
摘要:
Disclosed are venting hole structures suitable for AC grounding planes in multichip modules (MCMs) and the like. Such structures may be constructed from alternating layers of metal and dielectric materials, such as copper and polyimide, respectively. The venting structures according to the present invention are formed in the metal layers of grounding planes and enable gases trapped within the underlying dielectric layers to escape (so as to prevent delamination) without disturbing the function of the AC grounding plane to provide controlled impedance characteristics for signal lines disposed above and below the grounding plane.
摘要:
Novel structures for capacitors which are capable of withstanding heat treatments to at least 400.degree. C. while providing low defect densities and low electrical series resistance in its electrodes are disclosed. In one embodiment of the present invention, a capacitor structure includes a bottom capacitor electrode formed of a first sub-layer of aluminum, a second sub-layer of tantalum nitride, and a third sub-layer of tantalum. The capacitor structure further includes a sputtered dielectric layer of tantalum pentoxide over the tantalum sub-layer of the bottom electrode. The resulting structure is anodized such that the underlying tantalum layer is fully anodized, and preferably such that a portion of the tantalum nitride layer is converted to a tantalum oxy-nitride. The tantalum nitride layer was discovered by the inventors to act as a good high temperature diffusion barrier for the aluminum, preventing the aluminum from migrating into the anodized tantalum pentoxide layer under high temperature processing conditions, where it would chemically reduce the tantalum atoms in the tantalum pentoxide layer and introduce conductive paths of tantalum in the dielectric (tantalum pentoxide) layer. The aluminum layer provides good electrical conductivity for the bottom electrode, and is anodized to fill any pinhole defects in the layers formed above it, thereby increasing manufacturing yields.
摘要:
Several inventive features for increasing the yield of substrate capacitors are disclosed. The inventive features relating to selective placement of insulating layers and patches around selected areas of the capacitor's main dielectric layer. These insulating layers and defects prevent certain manufacturing processing steps from creating pin-hole defects in the main dielectric layer. The inventive features are suitable for any type of material for the main dielectric layer, and are particularly suited to anodized dielectric layers.
摘要:
An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides, with the patterned layers connected by a through via or post process. The two power/ground wrap substrates may be formed separately or from one substrate which is bent into a desired form (e.g., a “U” shape). The two power/ground substrates are maintained in their proper alignment relative to the signal core and to each other by edge connectors which are also connected to the signal core's intermediary power/ground plane.
摘要:
Methods for forming multilayer circuit structures are disclosed. In some embodiments, conductive layers, dielectric layers and conductive posts can be formed on both sides of a circuitized core structure. The conductive posts are disposed in the dielectric layers and can be stacked to form a generally vertical conduction pathway which passes at least partially through a multilayer circuit structure. The formed multilayer circuit structures can occupy less space than corresponding multilayer circuit structures with stacked via structures.