公开(公告)号：US08803333B2

公开(公告)日：2014-08-12

申请号：US13544746

申请日：2012-07-09

申请人： Chen-Hua Yu ,  Da-Yuan Shih ,  Chih-Hang Tung

发明人： Chen-Hua Yu ,  Da-Yuan Shih ,  Chih-Hang Tung

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L23/488

CPC分类号： H01L23/48 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/488 ,  H01L23/52 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/11466 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/1184 ,  H01L2224/13005 ,  H01L2224/13019 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13669 ,  H01L2224/13673 ,  H01L2224/13676 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/2919 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81205 ,  H01L2224/8183 ,  H01L2224/81895 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/206 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： A three dimensional (3D) chip stack includes a first chip bonded to a second chip. The first chip includes a first bump structure overlying the first substrate, and the second chip includes a second bump structure overlying the second substrate. The first bump structure is attached to the second bump structure, and a joining region is formed between the first bump structure and the second bump structure. The joining region is a solderless region which includes a noble metal.

摘要翻译： 三维（3D）芯片堆叠包括结合到第二芯片的第一芯片。 第一芯片包括覆盖第一基板的第一凸块结构，并且第二芯片包括覆盖第二基板的第二凸块结构。 第一凸块结构附接到第二凸块结构，并且在第一凸块结构和第二凸块结构之间形成接合区域。 接合区域是包括贵金属的无焊区域。

公开(公告)号：US20130207239A1

公开(公告)日：2013-08-15

申请号：US13370127

申请日：2012-02-09

申请人： Chen-Hua Yu ,  Da-Yuan Shih

发明人： Chen-Hua Yu ,  Da-Yuan Shih

IPC分类号： H01L29/02

CPC分类号： H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1131 ,  H01L2224/1134 ,  H01L2224/114 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/11616 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/15787 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2224/10125 ,  H01L2224/10155 ,  H01L2924/00

摘要： A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.

摘要翻译： 提供一种用于防止裂纹的系统和方法。 一个实施例包括将裂缝塞子放置在半导体管芯和衬底之间的连接中。 裂缝止动器可以是中空或实心圆筒的形状，并且可以放置成防止任何裂纹通过裂缝塞子传播。

公开(公告)号：US09230932B2

公开(公告)日：2016-01-05

申请号：US13370127

申请日：2012-02-09

申请人： Chen-Hua Yu ,  Da-Yuan Shih

发明人： Chen-Hua Yu ,  Da-Yuan Shih

IPC分类号： H01L23/544 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1131 ,  H01L2224/1134 ,  H01L2224/114 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/11616 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/15787 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2224/10125 ,  H01L2224/10155 ,  H01L2924/00

摘要： A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.

摘要翻译： 提供一种用于防止裂纹的系统和方法。 一个实施例包括将裂缝塞子放置在半导体管芯和衬底之间的连接中。 裂缝止动器可以是中空或实心圆筒的形状，并且可以放置成防止任何裂纹通过裂缝塞子传播。

公开(公告)号：US20130037950A1

公开(公告)日：2013-02-14

申请号：US13206694

申请日：2011-08-10

申请人： Chun Hui Yu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Chen-Hua Yu ,  Da-Yuan Shih

发明人： Chun Hui Yu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Chen-Hua Yu ,  Da-Yuan Shih

IPC分类号： H01L23/485 ,  H01L21/82 ,  H01L21/56

CPC分类号： H01L23/481 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76805 ,  H01L21/76838 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8203 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/83005

摘要： A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.

摘要翻译： 多芯片晶片级封装包括三个堆叠的半导体管芯。 第一半导体管芯被嵌入在第一光敏材料层中。 第二半导体管芯堆叠在第一半导体管芯的顶部上，其中第二半导体管芯与第一半导体管芯面对面连接。 第三半导体管芯背靠背连接到第二半导体管芯。 第二半导体管芯和第三半导体管芯都嵌入第二光敏材料层。 多芯片晶片级封装还包括形成在第一光敏材料层和第二光敏材料层中的多个通过组装通孔。

公开(公告)号：US20130040423A1

公开(公告)日：2013-02-14

申请号：US13206602

申请日：2011-08-10

申请人： Chih-Hang Tung ,  Chun Hui Yu ,  Chen-Hua Yu ,  Da-Yuan Shih

发明人： Chih-Hang Tung ,  Chun Hui Yu ,  Chen-Hua Yu ,  Da-Yuan Shih

IPC分类号： H01L21/56 ,  H01L21/82

CPC分类号： H01L25/50 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02311 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/08146 ,  H01L2224/12105 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/03

摘要： A method of multi-chip wafer level packaging comprises forming a reconfigured wafer using a plurality of photo-sensitive material layers. A plurality of semiconductor chips and wafers are embedded in the photo-sensitive material layers. Furthermore, a variety of through assembly vias are formed in the photo-sensitive material layers. Each semiconductor chip embedded in the photo-sensitive material layers is connected to input/output pads through connection paths formed by the through assembly vias.

摘要翻译： 多芯片晶片级封装的方法包括使用多个感光材料层形成重新配置的晶片。 多个半导体芯片和晶片被嵌入到感光材料层中。 此外，在感光材料层中形成各种贯穿组装通孔。 嵌入在感光材料层中的每个半导体芯片通过由通孔组装通孔形成的连接路径连接到输入/输出焊盘。

公开(公告)号：US20120061059A1

公开(公告)日：2012-03-15

申请号：US13033840

申请日：2011-02-24

申请人： Yi-Li HSIAO ,  Chen-Hua Yu ,  Da-Yuan Shih ,  Chih-Hang Tung ,  Chun Hui Yu

发明人： Yi-Li HSIAO ,  Chen-Hua Yu ,  Da-Yuan Shih ,  Chih-Hang Tung ,  Chun Hui Yu

IPC分类号： F28D15/00

CPC分类号： F28D15/02 ,  H01L23/34 ,  H01L23/473 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/0401

摘要： An apparatus for cooling a stacked die package comprises a first die provided above a substrate; a second die above the first die; a cooling fluid in fluid communication with the first die and the second die, the cooling fluid for absorbing thermal energy from the first and the second die; a housing containing the first and second dies, the housing sealing the first and second dies from an environment, wherein the housing further includes a first opening and a second opening, the first and second openings being vertically displaced from one another; a conduit having one end connected to the first opening and the other end connected to the second opening, the conduit allowing the cooling liquid to circulate from the first opening to the second opening; a first temperature sensor being arranged to provide an output that is dependent on a local temperature at the first opening; and a second temperature sensor being arranged to provide an output that is dependent on a local temperature at the second opening, wherein the outputs of the first and second temperature sensors relative to each other are indicative of a level of the cooling fluid.

摘要翻译： 一种用于冷却堆叠的管芯封装的设备，包括设置在衬底上的第一管芯; 第一个模具上方的第二个模具; 与第一模具和第二模具流体连通的冷却流体，用于从第一模具和第二模具吸收热能的冷却流体; 壳体，其包含第一和第二模具，所述壳体将环境中的第一和第二模具密封，其中所述壳体还包括第一开口和第二开口，所述第一和第二开口彼此垂直移位; 导管，其一端连接到第一开口，另一端连接到第二开口，导管允许冷却液从第一开口循环到第二开口; 第一温度传感器被布置成提供依赖于第一开口处的局部温度的输出; 并且第二温度传感器被布置成提供取决于第二开口处的局部温度的输出，其中第一和第二温度传感器相对于彼此的输出指示冷却流体的水平。

公开(公告)号：US08754514B2

公开(公告)日：2014-06-17

申请号：US13206694

申请日：2011-08-10

申请人： Chun Hui Yu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Chen-Hua Yu ,  Da-Yuan Shih

发明人： Chun Hui Yu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Chen-Hua Yu ,  Da-Yuan Shih

IPC分类号： H01L23/02 ,  H01L21/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76805 ,  H01L21/76838 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8203 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/83005

摘要： A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.

摘要翻译： 多芯片晶片级封装包括三个堆叠的半导体管芯。 第一半导体管芯被嵌入在第一光敏材料层中。 第二半导体管芯堆叠在第一半导体管芯的顶部上，其中第二半导体管芯与第一半导体管芯面对面连接。 第三半导体管芯背靠背连接到第二半导体管芯。 第二半导体管芯和第三半导体管芯都嵌入第二光敏材料层。 多芯片晶片级封装还包括形成在第一光敏材料层和第二光敏材料层中的多个通过组装通孔。

公开(公告)号：US20130241083A1

公开(公告)日：2013-09-19

申请号：US13421040

申请日：2012-03-15

申请人： Chen-Hua Yu ,  Da-Yuan Shih ,  Chih-Hang Tung

发明人： Chen-Hua Yu ,  Da-Yuan Shih ,  Chih-Hang Tung

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L23/49811 ,  H01L21/44 ,  H01L21/441 ,  H01L21/4853 ,  H01L23/48 ,  H01L23/52 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/42 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/1134 ,  H01L2224/13005 ,  H01L2224/13011 ,  H01L2224/13016 ,  H01L2224/13027 ,  H01L2224/13078 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1411 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48611 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/4911 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83411 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2224/45124 ,  H01L2924/00011 ,  H01L2924/206 ,  H01L2224/05147 ,  H01L2224/05144 ,  H01L2224/05164 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/05552

摘要： Disclosed embodiments include wire joints and methods of forming wire joints that can enable realization of fine pitch joints and collapse control for various packages. A first embodiment is a structure comprising a first substrate, a second substrate, and a wire joint. The first substrate comprises a first bonding surface, and the second substrate comprises a second bonding surface. The first bonding surface is opposite and faces the second bonding surface. The wire joint is attached to and between the first bonding surface and the second bonding surface.

摘要翻译： 公开的实施例包括线接头和形成线接头的方法，其可以实现细间距接头和各种包装件的塌陷控制。 第一实施例是包括第一基板，第二基板和线接头的结构。 第一衬底包括第一接合表面，并且第二衬底包括第二接合表面。 第一接合表面相对并面向第二接合表面。 线接头附接到第一接合表面和第二接合表面之间。

公开(公告)号：US08476770B2

公开(公告)日：2013-07-02

申请号：US13178345

申请日：2011-07-07

申请人： Tung-Liang Shao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Da-Yuan Shih

发明人： Tung-Liang Shao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Da-Yuan Shih

IPC分类号： H01L23/48

CPC分类号： H01L21/76802 ,  B29C43/04 ,  B29C43/18 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/19 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/83005

摘要： Methods and apparatus for forming through vias in an integrated circuit package are disclosed. An apparatus is disclosed, having a substrate having one or more bond pad terminals for receiving electrical connections on at least one surface; an encapsulation layer covering the at least one surface of the substrate and having a first thickness; a plurality of through vias extending through the encapsulation layer and positioned in correspondence with at least one of the one or more bond pad terminals; conductor material disposed within the plurality of through vias to form electrical connectors within the plurality of through vias; and at least one external terminal disposed on a surface of the encapsulation layer, electrically coupled to one of the one or more bond pad terminals by an electrical connector in at least one of the plurality of through vias. Package arrangements and methods for the through vias are disclosed.

摘要翻译： 公开了用于在集成电路封装中形成通孔的方法和装置。 公开了一种装置，其具有一个基板，该基板具有一个或多个接合焊盘端子，用于在至少一个表面上接收电连接; 覆盖所述衬底的所述至少一个表面并具有第一厚度的封装层; 多个通孔，其延伸穿过所述封装层并且与所述一个或多个接合焊盘端子中的至少一个相对应地定位; 导体材料设置在所述多个通孔内，以在所述多个通孔内形成电连接器; 以及设置在所述封装层的表面上的至少一个外部端子，通过所述多个通孔中的至少一个通孔中的电连接器电耦合到所述一个或多个接合焊盘端子中的一个。 公开了通孔的封装结构和方法。

公开(公告)号：US20130009319A1

公开(公告)日：2013-01-10

申请号：US13178345

申请日：2011-07-07

申请人： Tung-Liang Shao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Da-Yuan Shih

发明人： Tung-Liang Shao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Da-Yuan Shih

IPC分类号： H01L23/48 ,  B29C43/04 ,  H01L21/56

CPC分类号： H01L21/76802 ,  B29C43/04 ,  B29C43/18 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/19 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/83005

摘要： Methods and apparatus for forming through vias in an integrated circuit package are disclosed. An apparatus is disclosed, having a substrate having one or more bond pad terminals for receiving electrical connections on at least one surface; an encapsulation layer covering the at least one surface of the substrate and having a first thickness; a plurality of through vias extending through the encapsulation layer and positioned in correspondence with at least one of the one or more bond pad terminals; conductor material disposed within the plurality of through vias to form electrical connectors within the plurality of through vias; and at least one external terminal disposed on a surface of the encapsulation layer, electrically coupled to one of the one or more bond pad terminals by an electrical connector in at least one of the plurality of through vias. Package arrangements and methods for the through vias are disclosed.

摘要翻译： 公开了用于在集成电路封装中形成通孔的方法和装置。 公开了一种装置，其具有一个基板，该基板具有一个或多个接合焊盘端子，用于在至少一个表面上接收电连接; 覆盖所述衬底的所述至少一个表面并具有第一厚度的封装层; 多个通孔，其延伸穿过所述封装层并且与所述一个或多个接合焊盘端子中的至少一个相对应地定位; 导体材料设置在所述多个通孔内，以在所述多个通孔内形成电连接器; 以及设置在所述封装层的表面上的至少一个外部端子，通过所述多个通孔中的至少一个通孔中的电连接器电耦合到所述一个或多个接合焊盘端子中的一个。 公开了通孔的封装结构和方法。