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    NON-VOLATILE MEMORY EXPRESS OVER FABRIC (NVMeOF) USING VOLUME MANAGEMENT DEVICE
    2.
    发明申请
    NON-VOLATILE MEMORY EXPRESS OVER FABRIC (NVMeOF) USING VOLUME MANAGEMENT DEVICE 审中-公开

    公开(公告)号：US20180337991A1

    公开(公告)日：2018-11-22

    申请号：US15599020

    申请日：2017-05-18

    Applicant: Intel Corporation

    Inventor： MOHAN J. KUMAR ,  MURUGASAMY K. NACHIMUTHU

    IPC: H04L29/08 ,  H04L12/24 ,  H04L29/06

    Abstract: Non-volatile Memory Express over Fabric (NVMeOF) using Volume Management Device (VMD) schemes and associated methods, systems and software. The schemes are implemented in a data center environment including compute resources in compute drawers and storage resources residing in pooled storage drawers that are communicatively couple via a fabric. Compute resources are composed as compute nodes or virtual machines/containers running on compute nodes to utilize remote storage devices in pooled storage drawers, while exposing the remote storage devices as local NVMe storage devices to software running on the compute nodes. This is facilitated by virtualizing the system's storage infrastructure through use of hardware-based components, firmware-based components, or a combination of hardware/firmware- and software-based components. The schemes support the use of remote NVMe storage devices using an NVMeOF protocol and/or use of non-NVMe storage devices using NVMe emulation.

    METHODS AND APPARATUS TO REDUCE STATIC AND DYNAMIC FRAGMENTATION IMPACT ON SOFTWARE-DEFINED INFRASTRUCTURE ARCHITECTURES
    4.
    发明申请
    METHODS AND APPARATUS TO REDUCE STATIC AND DYNAMIC FRAGMENTATION IMPACT ON SOFTWARE-DEFINED INFRASTRUCTURE ARCHITECTURES 审中-公开

    公开(公告)号：US20180026868A1

    公开(公告)日：2018-01-25

    申请号：US15655846

    申请日：2017-07-20

    Applicant: INTEL CORPORATION

    Inventor： FRANCESC GUIM BERNAT ,  SUSANNE M. BALLE ,  DANIEL RIVAS BARRAGAN ,  JOHN CHUN KWOK LEUNG ,  SURAJ PRABHAKARAN ,  MURUGASAMY K. NACHIMUTHU ,  SLAWOMIR PUTYRSKI

    IPC: H04L12/26

    Abstract: Techniques for reducing fragmentation in software-defined infrastructures are described. A compute node, including one or more processor circuits, may be configured to access one or more remote resources via a fabric, the compute node may be configured to receive a dynamic tolerated fragmentation for the one or more remote resources. The compute node may be configured to monitor the performance of the one or more remote resources. For example, the compute node may be configured to monitor if one or more of the monitored resources were to exceed a threshold bandwidth or latency range as defined by the dynamic tolerated fragmentation. The compute node may be configured to determine that the monitored performance of the one or more remote resources is outside a threshold defined by the dynamic tolerated fragmentation. If one or more of the remote resources is outside the threshold, for a predetermined period of time, or otherwise, the compute node may be configured to determine so and take appropriate measures, such as generating a message indicating that performance of the one or more remote resources is outside a threshold defined by the dynamic tolerated fragmentation. Other embodiments are described and claimed.

    UNIFIED HARDWARE AND SOFTWARE TWO-LEVEL MEMORY
    5.
    发明申请
    UNIFIED HARDWARE AND SOFTWARE TWO-LEVEL MEMORY 审中-公开

    公开(公告)号：US20190138457A1

    公开(公告)日：2019-05-09

    申请号：US16235504

    申请日：2018-12-28

    Applicant: INTEL CORPORATION

    Inventor： MOHAN J. KUMAR ,  MURUGASAMY K. NACHIMUTHU

    IPC: G06F12/1009 ,  G06F3/06

    Abstract: Unified hardware and software two-level memory mechanisms and associated methods, systems, and software. Data is stored on near and far memory devices, wherein an access latency for a near memory device is less than an access latency for a far memory device. The near memory devices store data in data units having addresses in a near memory virtual address space, while the far memory devices store data in data units having addresses in a far memory address space, with a portion of the data being stored on both near and far memory devices. In response to memory read access requests, a determination is made to where data corresponding to the request is located on a near memory device, and if so the data is read from the near memory device; otherwise, the data is read from a far memory device. Memory access patterns are observed, and portions of far memory that are frequently accessed are copied to near memory to reduce access latency for subsequent accesses.

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