公开(公告)号：US08742579B2

公开(公告)日：2014-06-03

申请号：US13405094

申请日：2012-02-24

Applicant: Reza A. Pagaila ,  Byung Tai Do ,  Shuangwu Huang

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Shuangwu Huang

IPC: H01L21/00

CPC classification number: H01L24/18 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1902 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

Abstract translation: 通过提供牺牲衬底并在牺牲衬底上沉积粘合剂层来制造半导体器件。 在粘合剂层上形成第一导电层。 聚合物柱形成在第一导电层上。 在聚合物柱上方形成第二导电层以产生具有内聚合物芯的导电柱。 半导体管芯或部件安装在衬底上。 密封剂沉积在半导体管芯或部件上并且围绕导电柱。 第一互连结构形成在密封剂的第一侧上。 第一互连结构电连接到导电柱。 去除牺牲基底和粘合剂层。 在与第一互连结构相对的密封剂的第二侧上形成第二互连结构。 第二互连结构电连接到导电柱。

公开(公告)号：US08735224B2

公开(公告)日：2014-05-27

申请号：US13102044

申请日：2011-05-05

Applicant: Byung Tai Do ,  Arnel Senosa Trasporto ,  Zigmund Ramirez Camacho

Inventor： Byung Tai Do ,  Arnel Senosa Trasporto ,  Zigmund Ramirez Camacho

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/49503 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace.

Abstract translation: 一种集成电路封装系统的制造方法，包括：提供具有凹部的具有顶部的端子; 在所述凹陷中施加电介质材料，所述电介质材料在其中形成间隙并暴露所述顶部的一部分; 在所述间隙内形成迹线并与所述顶部直接接触，所述迹线在所述电介质材料的上表面上横向延伸; 并通过轨迹将集成电路连接到终端。

公开(公告)号：US08729694B2

公开(公告)日：2014-05-20

申请号：US13171341

申请日：2011-06-28

Applicant: Byung Tai Do ,  Reza A. Pagaila

Inventor： Byung Tai Do ,  Reza A. Pagaila

IPC: H01L23/48

CPC classification number: H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is formed on the die. The trench extends to and is continuous with the via. A first conductive layer is deposited in the trench and via to form conductive TSV. The first conductive layer is conformally applied or completely fills the trench and via. The trench has a larger area than the vias which accelerates formation of the first conductive layer. A second conductive layer is deposited over a front surface of the die. The second conductive layer is electrically connected to the first conductive layer. The first and second conductive layers can be formed simultaneously. A portion of a back surface of the wafer is removed to expose the first conductive layer. The die can be stacked and electrically interconnected through the TSVs.

Abstract translation: 半导体晶片具有由周边区域分离的多个半导体管芯。 在晶片的周边区域形成沟槽。 在管芯上形成通孔。 沟槽延伸到并且与通孔连续。 第一导电层沉积在沟槽和通孔中以形成导电TSV。 第一导电层被保形地施加或完全填充沟槽和通孔。 沟槽具有比加速第一导电层的形成的通孔更大的面积。 第二导电层沉积在管芯的前表面上。 第二导电层电连接到第一导电层。 第一和第二导电层可以同时形成。 去除晶片的后表面的一部分以露出第一导电层。 模具可以通过TSV堆叠和电互连。

公开(公告)号：US20140131869A1

公开(公告)日：2014-05-15

申请号：US14160796

申请日：2014-01-22

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.

Abstract translation: 半导体器件具有具有管芯凸块焊盘的半导体管芯和具有轨迹线和集成凸块焊盘的衬底。 导电凸块材料沉积在衬底凸块焊盘或模具凸块焊盘上。 半导体管芯安装在衬底上，使得凸块材料设置在管芯凸块焊盘和衬底凸块焊盘之间。 凸块材料在芯片凸块焊盘或基板凸块焊盘周围没有焊接掩模回流以形成互连。 凸块材料在管芯凸块焊盘或衬底凸块焊盘的占用面积内自我限制。 在回流之前，凸起材料可以浸入助熔剂溶液中以增加润湿性。 或者，互连包括不可熔基底和可熔盖。 选择凸起材料的体积，使得表面张力在回流期间保持凸块内的凸起材料的自我约束。

公开(公告)号：US08723338B2

公开(公告)日：2014-05-13

申请号：US13586178

申请日：2012-08-15

Applicant: Henry Descalzo Bathan ,  Zigmund Ramirez Camacho ,  Emmanuel Espiritu

Inventor： Henry Descalzo Bathan ,  Zigmund Ramirez Camacho ,  Emmanuel Espiritu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/49 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/4554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/83856 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an array of leads having a jumper lead and a covered contact; coupling an insulated bonding wire between the jumper lead and the covered contact; attaching an integrated circuit die over the covered contact; and coupling a bond wire between the integrated circuit die and the jumper lead including coupling the integrated circuit die to the covered contact through the insulated bonding wire.

Abstract translation: 一种制造集成电路封装系统的方法，包括：提供具有跳线和覆盖触点的引线阵列; 将绝缘接合线耦合在跳线和覆盖触点之间; 将集成电路管芯覆盖在覆盖的触点上; 并且在所述集成电路管芯和所述跨接引线之间耦合接合线，包括通过所述绝缘接合线将所述集成电路管芯连接到所述覆盖接触点。

公开(公告)号：US08723310B2

公开(公告)日：2014-05-13

申请号：US13526877

申请日：2012-06-19

Applicant: YiSu Park ,  KyungHoon Lee ,  Joungln Yang ,  SangMi Park ,  DaeSik Choi

Inventor： YiSu Park ,  KyungHoon Lee ,  Joungln Yang ,  SangMi Park ,  DaeSik Choi

IPC: H01L23/10

CPC classification number: H01L23/3135 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A method of manufacture of an integrated circuit packaging system includes providing a substrate; connecting an integrated circuit die; forming a molding having a temperature-dependent characteristic directly on the top surface of the substrate; and forming a coupling encapsulation having a coupled characteristic different from the temperature-dependent characteristic directly on the molding forms an encapsulation boundary between the coupling encapsulation and the molding.

Abstract translation: 一种集成电路封装系统的制造方法，包括：提供基板; 连接集成电路管芯; 在衬底的顶表面上直接形成具有温度依赖特性的模制品; 并且形成具有与温度相关特性不同的耦合特性的耦合封装，直接在模塑件上形成耦合封装和模制件之间的封装边界。

公开(公告)号：US08723302B2

公开(公告)日：2014-05-13

申请号：US12333298

申请日：2008-12-11

Applicant: Harry Chandra ,  Flynn Carson

Inventor： Harry Chandra ,  Flynn Carson

IPC: H01L23/02 ,  H01L21/44

CPC classification number: H01L23/5385 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package system includes: forming a base stacking package including: fabricating a base substrate, mounting an integrated circuit on the base substrate, positioning an input/output expansion substrate, having access ports around an inner array area, over the integrated circuit, and injecting a molding compound on the base substrate, the integrated circuit, and the input/output expansion substrate; and mounting a top package on the input/output expansion substrate.

Abstract translation: 一种集成电路封装系统，包括：形成基底堆叠封装，包括：制造基底基板，将集成电路安装在基底基板上，在集成电路上定位具有围绕内部阵列区域的入口的输入/输出扩展基板， 在基底基板，集成电路和输入输出扩展基板上注入模塑料; 并将顶部封装安装在输入/输出扩展基板上。

公开(公告)号：US08722457B2

公开(公告)日：2014-05-13

申请号：US11965383

申请日：2007-12-27

Applicant: Zigmund R. Camacho ,  Dioscoro A. Merilo ,  Lionel Chien Hui Tay ,  Henry Descalzo Bathan

Inventor： Zigmund R. Camacho ,  Dioscoro A. Merilo ,  Lionel Chien Hui Tay ,  Henry Descalzo Bathan

IPC: H01L21/00

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49861 ,  H01L23/5385 ,  H01L24/48 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a semiconductor package, a substrate has an active surface containing a plurality of active circuits. An adhesive layer is formed over the active surface of the substrate, and a known good unit (KGU) is mounted to the adhesive layer. An interconnect structure electrically connects the KGU and active circuits on the substrate. The interconnect structure includes a wire bond between a contact pad on the substrate and a contact pad on the KGU, a redistribution layer on a back surface of the substrate, opposite the active surface, a through hole via (THV) through the substrate that electrically connects the redistribution layer and wire bond, and solder bumps formed in electrical contact with the redistribution layer. The KGU includes a KGU substrate for supporting the KGU, a semiconductor die disposed over the KGU substrate, and an encapsulant formed over the semiconductor die.

Abstract translation: 在半导体封装中，衬底具有包含多个有源电路的有源表面。 在基板的有效表面上形成粘合剂层，并且将已知的良好单元（KGU）安装到粘合剂层上。 互连结构将KGU和衬底上的有源电路电连接。 所述互连结构包括在所述衬底上的接触焊盘和所述KGU上的接触焊盘之间的引线接合，所述衬底的背面上的与所述有源表面相对的再分布层，穿过所述衬底的通孔通孔（THV） 连接再分布层和引线键合，以及与再分布层电接触形成的焊料凸块。 KGU包括用于支撑KGU的KGU基板，设置在KGU基板上的半导体管芯，以及形成在半导体管芯上的密封剂。

公开(公告)号：US20140127858A1

公开(公告)日：2014-05-08

申请号：US14154049

申请日：2014-01-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each including a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.

Abstract translation: 嵌入式半导体管芯封装通过使用粘合剂将框架载体安装到临时载体上而制成。 框架载体包括每个包括围绕腔的引线框架互连结构的管芯安装位置。 半导体管芯设置在每个腔中。 将密封剂沉积在模具上的空腔中。 封装互连结构形成在引线框架互连结构和密封剂上。 封装互连结构和引线框互连结构电连接到管芯。 帧载体被分成单独的嵌入式芯片封装。 半导体管芯可以垂直堆叠或并排放置在腔内。 嵌入式管芯封装可以通过引线框互连结构堆叠并电互连。 半导体器件可以安装到嵌入式裸片封装并且通过引线框互连结构电连接到裸片。

公开(公告)号：US08710670B2

公开(公告)日：2014-04-29

申请号：US13326116

申请日：2011-12-14

Applicant: MinJung Kim ,  DaeSik Choi ,  Wonll Kwon

Inventor： MinJung Kim ,  DaeSik Choi ,  Wonll Kwon

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/02175 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05111 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05601 ,  H01L2224/05611 ,  H01L2224/0579 ,  H01L2224/058 ,  H01L2224/06181 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11901 ,  H01L2224/13009 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16238 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81365 ,  H01L2224/8185 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a wafer substrate having an active side containing a contact; forming a through silicon via extending through the wafer substrate electrically connected to the contact having a via width; forming a first coupling feature extending from a top side of the through silicon via; and forming a second coupling feature on the side of the through silicon via opposite the first coupling feature.

Abstract translation: 一种集成电路封装系统的制造方法，包括：提供具有包含触点的有源侧的晶片衬底; 通过延伸通过所述晶片衬底电连接到具有通孔宽度的所述触点来形成穿硅; 形成从所述通孔硅通孔的顶侧延伸的第一耦合特征; 以及通过与所述第一耦合特征相反的方式在所述贯通硅的侧面上形成第二耦合特征。