公开(公告)号：US6163070A

公开(公告)日：2000-12-19

申请号：US977669

申请日：1997-11-24

Applicant: Ryuichiro Mori

Inventor： Ryuichiro Mori

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/50 ,  H01L25/10 ,  H01L25/11 ,  H05K3/36 ,  H05K13/04 ,  H01L23/02

CPC classification number: H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/05553 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15192 ,  H05K3/363 ,  H05K13/046 ,  H05K2201/055 ,  H05K2201/10462 ,  H05K2201/10484 ,  H05K2201/10681 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A semiconductor package having a plurality of electrodes arranged along one side of a rectangular semiconductor element; a plurality of wirings, one end of the wiring to be electrically connected with the electrode being arranged adjacent to the electrode and the other end of the wiring being exposed from an opening for external connection; a conductive member provided on the opening for external connection; a flexible wiring substrate on which the semiconductor element is mounted, and the wiring and the conductive member are arranged; and a sealing resin for sealing, except for the conductive member, the semiconductor element and a periphery of the semiconductor element. The semiconductor package can be connected in a horizontal or inclined condition with respect to the substrate for packaging by folding the flexible wiring substrate.

Abstract translation: 一种半导体封装，具有沿矩形半导体元件的一侧布置的多个电极; 多个布线，与电极电连接的布线的一端布置成与电极相邻，并且布线的另一端从用于外部连接的开口露出; 设置在所述开口上用于外部连接的导电构件; 布置有半导体元件的柔性布线基板，布线和导电部件布置; 以及用于密封除了导电构件，半导体元件和半导体元件的周边之外的密封树脂。 半导体封装可以通过折叠柔性布线基板而相对于用于封装的基板以水平或倾斜状态连接。

公开(公告)号：US6011741A

公开(公告)日：2000-01-04

申请号：US121348

申请日：1998-07-23

Applicant: Robert F. Wallace ,  Robert D. Norman ,  Eliyahou Harari

Inventor： Robert F. Wallace ,  Robert D. Norman ,  Eliyahou Harari

IPC: G06F3/06 ,  G06F12/00 ,  G06F13/00 ,  G06F13/38 ,  G06K7/00 ,  G11C5/00 ,  G11C5/02 ,  G11C7/00 ,  G11C16/04 ,  G11C16/06 ,  H05K1/14

CPC classification number: G06F3/0601 ,  G06F13/385 ,  G06K19/07732 ,  G06K19/07741 ,  G06K19/07743 ,  G06K7/0047 ,  G11C5/04 ,  H05K1/141 ,  H05K7/1431 ,  G06F2003/0694 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83385 ,  H05K2201/10159 ,  H05K2201/10462 ,  H05K2201/10484 ,  H05K2203/1572 ,  H05K3/3421

Abstract: A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.

公开(公告)号：US5867417A

公开(公告)日：1999-02-02

申请号：US907111

申请日：1997-08-06

Applicant: Robert F. Wallace ,  Robert D. Norman ,  Eliyahou Harari

Inventor： Robert F. Wallace ,  Robert D. Norman ,  Eliyahou Harari

IPC: G06F3/06 ,  G06F12/00 ,  G06F13/00 ,  G06F13/38 ,  G06K7/00 ,  G11C5/00 ,  G11C5/02 ,  G11C7/00 ,  G11C16/04 ,  G11C16/06 ,  H05K1/14

CPC classification number: G06F3/0601 ,  G06F13/385 ,  G06K19/07732 ,  G06K19/07741 ,  G06K19/07743 ,  G06K7/0047 ,  G11C5/04 ,  H05K1/141 ,  H05K7/1431 ,  G06F2003/0694 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83385 ,  H05K2201/10159 ,  H05K2201/10462 ,  H05K2201/10484 ,  H05K2203/1572 ,  H05K3/3421

Abstract: A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.

公开(公告)号：US5227664A

公开(公告)日：1993-07-13

申请号：US710642

申请日：1991-06-05

Applicant: Sugano Toshio ,  Tsukui Seiichirou ,  Suzuki Shigeru

Inventor： Sugano Toshio ,  Tsukui Seiichirou ,  Suzuki Shigeru

IPC: H01L23/50 ,  H01L25/10 ,  H05K1/00 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

CPC classification number: H05K1/141 ,  H01L23/50 ,  H01L25/105 ,  H01R12/721 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H05K1/0289 ,  H05K1/181 ,  H05K2201/09336 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10484 ,  H05K2201/10689 ,  H05K2203/1572 ,  H05K3/366

Abstract: In an SIP type module of the type wherein memory ICs are mounted to both surfaces of a substrate, the present invention provides a face package type memory module wherein packaging is made in an inclined direction in place of vertical packaging of the prior art technique and only the memory ICs mounted to the upper surface side of the substrate are deviated to the positions closer to the end portion of the substrate in order to drastically reduce the packaging height.

Abstract translation: 在其中存储器IC被安装到基板的两个表面的类型的SIP型模块中，本发明提供一种面包装型存储模块，其中以倾斜方向制造包装，代替现有技术的垂直包装，并且仅仅 安装到基板的上表面侧的存储器IC偏离到靠近基板的端部的位置，以显着降低封装高度。

公开(公告)号：US4907978A

公开(公告)日：1990-03-13

申请号：US266106

申请日：1988-11-02

Applicant: David C. Bowen

Inventor： David C. Bowen

IPC: H01R12/50 ,  H05K3/30

CPC classification number: H05K3/308 ,  H01R12/716 ,  H05K2201/10189 ,  H05K2201/10484 ,  H05K2201/10878 ,  Y10T29/49139

Abstract: A connector is provided for mounting on a circuit board. The connector includes a body member and rows of first and second electrical contact pins coupled to the body member. The first contact pins are configured to extend downwardly below a bottom wall of the body member so that they align with the bottom wall to define an acute included angle therebetween. The second contact pins are configured to extend downwardly below the bottom wall in splayed relation to the first electrical contact pins and are aligned with the bottom wall to define an obtuse included angle therebetween. The first and second contact pins are made of spring material and cooperate to define a spring clip for yieldably drawing the bottom wall of the body member into seating engagement with the circuit board upon insertion of the first and second electrical contact pins into a pair of pin-receiving apertures formed in the circuit board.

Abstract translation: 提供一个用于安装在电路板上的连接器。 连接器包括本体构件和联接到主体构件的第一和第二电接触销的行。 第一接触销构造成在主体构件的底壁下方向下延伸，使得它们与底壁对准以在其间限定锐角。 第二接触销构造成以与第一电接触销相对的方式向下延伸到底壁下方并且与底壁对准以在其间限定钝角。 第一和第二接触销由弹簧材料制成并且协作以限定弹簧夹，用于在将第一和第二电触针插入一对销时可弹性地拉动主体部件的底壁与电路板就座接合 - 形成在电路板中的接收孔。

公开(公告)号：US4818823A

公开(公告)日：1989-04-04

申请号：US70343

申请日：1987-07-06

Applicant: Robert F. Bradley

Inventor： Robert F. Bradley

IPC: H05K1/18 ,  H05K3/28 ,  H05K3/30 ,  H05K3/32

CPC classification number: H05K3/284 ,  H05K3/305 ,  H05K3/321 ,  H05K1/181 ,  H05K2201/0373 ,  H05K2201/10462 ,  H05K2201/10484 ,  H05K2201/10628 ,  H05K2201/10636 ,  H05K2201/10651 ,  H05K2201/10689 ,  H05K2201/10795 ,  H05K2201/10984 ,  H05K2203/0191 ,  H05K2203/1311 ,  Y02P70/611 ,  Y02P70/613

Abstract: A surface mounting method which utilizes an adhesive component to mount the electrical components to a printed circuit board instead of solder and which includes the use, between the contacting surfaces, of a flowable, corrosion-resistant material which bridges contact imperfections and penetrates surface films. The method may also be implemented to connect two electrical conductors.

Abstract translation: 一种表面安装方法，其利用粘合剂部件将电气部件安装到印刷电路板而不是焊料，并且包括在接触表面之间使用桥接接触缺陷并渗透表面膜的可流动的耐腐蚀材料。 还可以实现该方法来连接两个电导体。

公开(公告)号：US4556266A

公开(公告)日：1985-12-03

申请号：US578712

申请日：1984-02-09

Applicant: Toshimitsu Sonobe

Inventor： Toshimitsu Sonobe

IPC: H01B7/08 ,  H01R11/00 ,  H01R11/01 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H05K7/08

CPC classification number: H05K3/368 ,  H01R12/523 ,  H05K2201/09709 ,  H05K2201/10136 ,  H05K2201/10424 ,  H05K2201/10484 ,  H05K3/3447

Abstract: A jumper wire material for connecting a pair of printed circuit wiring boards and having, in addition, a function to serve as a spacer for holding the printed circuit wiring boards in a mutually spaced relationship, the jumper wire material being constructed with core wires arranged in parallel with each other at a predetermined pitch, an insulative covering of a solid and non-flexible plastic material, and ridges projectively provided in parallel with each other on a pair of mutually opposed side surfaces of the insulative covering, and extending along the core wires.

Abstract translation: 一种用于连接一对印刷电路布线板的跨接线材料，并且还具有用作间隔件的功能，用于以相互间隔的关系保持印刷电路布线板，所述跨接线材料由芯线构成，芯线布置在 以预定间距彼此平行，固体和非柔性塑料材料的绝缘覆盖物，以及在绝缘覆盖物的一对相互相对的侧表面上彼此平行地投影设置并且沿芯线延伸的脊部 。

公开(公告)号：US09814139B2

公开(公告)日：2017-11-07

申请号：US15124499

申请日：2015-02-27

Applicant: Sony Corporation

Inventor： Toshihiko Watanabe

IPC: H05K1/16 ,  H05K1/11 ,  H05K3/34 ,  H01L23/498 ,  H01L21/48 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H05K1/03 ,  H01L33/48

CPC classification number: H05K1/116 ,  H01L21/486 ,  H01L23/49827 ,  H01L33/48 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1531 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/112 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/3436 ,  H05K3/3447 ,  H05K3/3489 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/09154 ,  H05K2201/0959 ,  H05K2201/09863 ,  H05K2201/10106 ,  H05K2201/10484 ,  H05K2203/1383 ,  H05K2203/1394 ,  Y02P70/613

Abstract: A mounting substrate includes a through-hole 13 formed in a substrate 10, a first land part 21, a second land part 31, a first component attaching part 22, a second component attaching part 32, a conductive layer 14, and a filling member 15 filled into a part of the through-hole 13. A shortest distance allowable value L0 from the center of the first land part 21 to a component 51 is determined on the basis of the volume Vh of a part of the through-hole 15 positioned above a top surface of the filling member 15 on the side of the first land part 21, the length L1 of the component 51 to be mounted to the first component attaching part 22, and the maximum allowable value of the inclination of the component 51 to be mounted to the first component attaching part 22 relative to the first surface 11 of the substrate 10.

公开(公告)号：US09480151B2

公开(公告)日：2016-10-25

申请号：US13574789

申请日：2011-01-31

Applicant: Margaretha Maria De Kok ,  Jeroen Van Den Brand ,  Gerardus Titus Van Heck

Inventor： Margaretha Maria De Kok ,  Jeroen Van Den Brand ,  Gerardus Titus Van Heck

IPC: H05K1/00 ,  H05K1/02 ,  H01L27/32 ,  H01L51/52 ,  H01R4/70 ,  H05K3/36 ,  H05B33/08 ,  H05B33/10 ,  H05K13/04 ,  H01L31/0392 ,  H01L31/042 ,  G09F9/00 ,  G09F19/22 ,  H01R4/04 ,  H01R12/70 ,  H05K1/03 ,  H05K1/14 ,  H05K1/18 ,  H05K3/32

CPC classification number: H05K1/0277 ,  G09F9/00 ,  G09F19/22 ,  H01L27/3293 ,  H01L31/0392 ,  H01L31/042 ,  H01L51/5203 ,  H01L2251/5338 ,  H01L2251/5361 ,  H01R4/04 ,  H01R4/70 ,  H01R12/7076 ,  H05B33/0896 ,  H05B33/10 ,  H05K1/0283 ,  H05K1/038 ,  H05K1/147 ,  H05K1/189 ,  H05K3/321 ,  H05K3/325 ,  H05K3/365 ,  H05K13/04 ,  H05K2201/029 ,  H05K2201/0311 ,  H05K2201/046 ,  H05K2201/083 ,  H05K2201/09081 ,  H05K2201/09281 ,  H05K2201/10106 ,  H05K2201/10287 ,  H05K2201/10484 ,  Y02E10/50 ,  Y10T29/4913

Abstract: An assembly of a plurality of tiles (1) with a carrier (40), wherein the tiles (1) comprise a foil (20) with an electro-physical transducer (10) and electrical connectors (24, 28) to said transducer. The tiles are mechanically and electrically coupled to the carrier, and the tiles overlay according to a fish scale pattern.

Abstract translation: 具有载体（40）的多个瓦片（1）的组件，其中瓦片（1）包括具有电 - 物理换能器（10）的箔（20）和到所述换能器的电连接器（24,28）。 瓦片机械地和电耦合到载体上，并且瓦片根据鱼鳞图案覆盖。

公开(公告)号：US09250403B2

公开(公告)日：2016-02-02

申请号：US14047910

申请日：2013-10-07

Applicant: Oracle International Corporation

Inventor： Hiren D. Thacker ,  Frankie Y. Liu ,  Robert David Hopkins, II ,  Jon Lexau ,  Xuezhe Zheng ,  Guoliang Li ,  Ivan Shubin ,  Ronald Ho ,  John E. Cunningham ,  Ashok V. Krishnamoorthy

IPC: G02B6/12 ,  G02B6/42 ,  H01L25/065 ,  H01L23/00 ,  H05K3/36

CPC classification number: G02B6/4274 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/72 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/72 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06534 ,  H01L2225/06589 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/37001 ,  H05K3/36 ,  H05K2201/10484 ,  H01L2924/00

Abstract: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a front surface of the optical integrated circuit by a top surface of the interposer, where the top surface faces the front surface of the integrated circuit and the front surface of the optical integrated circuit. Furthermore, the integrated circuit and the optical integrated circuit may be on a same side of the interposer. By integrating the optical integrated circuit and the integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.

Abstract translation: 芯片封装包括与芯片封装中的每一个相邻的光学集成电路（例如混合集成电路）和集成电路。 集成电路包括诸如存储器或处理器的电路，并且光学集成电路传送具有非常高带宽的光信号。 此外，集成电路的前表面通过插入件的顶表面电耦合到光集成电路的前表面，其中顶表面面向集成电路的前表面和光集成电路的前表面 。 此外，集成电路和光集成电路可以在插入器的同一侧上。 通过将光集成电路和集成电路集成在一起，与具有电互连的芯片封装相比，芯片封装可以有助于提高性能。