公开(公告)号：US11756826B2

公开(公告)日：2023-09-12

申请号：US17473679

申请日：2021-09-13

申请人： Micron Technology, Inc.

发明人： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC分类号： H01L21/768 ,  H01L21/762 ,  H10B43/40 ,  H10B43/20 ,  H10B43/35 ,  H10B43/50

CPC分类号： H01L21/76802 ,  H01L21/762 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76877 ,  H10B43/20 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

摘要： A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.

公开(公告)号：US20230276620A1

公开(公告)日：2023-08-31

申请号：US18144650

申请日：2023-05-08

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Zhong Zhang ,  Zhongwang Sun ,  Wenxi Zhou ,  Zhiliang Xia

IPC分类号： H10B41/20 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC分类号： H10B41/20 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

摘要： In an example, a three-dimensional (3D) memory device includes a memory array structure including a first and a second memory array structures, a staircase structure between the first and a second memory array structures in a first lateral direction and including a first and a second staircase zones, and a bridge structure between the first and second staircase zones in a second lateral direction perpendicular to the first lateral direction. Each of the first and second staircase zones includes first and second sub-staircases arranged alternately. Each first sub-staircase includes ascending stairs at different depths. Each second sub-staircase includes descending stairs at different depths. At least one stair in each of the first and second sub-staircases is connected to at least one of the first and second memory array structures through the bridge structure.

公开(公告)号：US11737281B2

公开(公告)日：2023-08-22

申请号：US17645133

申请日：2021-12-20

申请人： Kioxia Corporation

发明人： Harumi Seki ,  Kensuke Ota ,  Masumi Saitoh

IPC分类号： H10B51/30 ,  H01L29/51 ,  H10B51/20 ,  H10B43/30 ,  H10B43/20 ,  H01L29/792

CPC分类号： H10B51/30 ,  H01L29/516 ,  H01L29/792 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20

摘要： A semiconductor memory device according to an embodiment includes: a semiconductor layer extending in a first direction; a first gate electrode layer; a first insulating layer between the semiconductor layer and the first gate electrode layer; a second insulating layer between the first insulating layer and the first gate electrode layer, the second insulating layer having a first portion containing a ferroelectric material; and a first layer between the first insulating layer and the second insulating layer, the first layer containing silicon, nitrogen, and fluorine, the first layer having a first region and a second region between the first region and the second insulating layer, the first layer having a second atomic ratio of nitrogen to silicon in the second region higher than a first atomic ratio of nitrogen to silicon in the first region, and the first layer having fluorine concentration higher than the second region.

公开(公告)号：US11737270B2

公开(公告)日：2023-08-22

申请号：US17897255

申请日：2022-08-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Junhyoung Kim ,  Jisung Cheon ,  Yoonhwan Son ,  Seungmin Lee

IPC分类号： H10B43/20 ,  H10B43/30 ,  H10B43/40

CPC分类号： H10B43/20 ,  H10B43/30 ,  H10B43/40

摘要： A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：US11735462B2

公开(公告)日：2023-08-22

申请号：US18088602

申请日：2022-12-25

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H10B20/20

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1579 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/30105 ,  H10B12/05 ,  H10B20/20

摘要： A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

公开(公告)号：US11730000B2

公开(公告)日：2023-08-15

申请号：US17493502

申请日：2021-10-04

申请人： Sunrise Memory Corporation

发明人： Eli Harari ,  Wu-Yi Chien

IPC分类号： H10B69/00 ,  H01L23/528 ,  H10B41/27 ,  H10B41/30 ,  H10B43/00 ,  H10B43/20 ,  H10B43/30 ,  G11C16/04 ,  C25B11/051 ,  C25B3/25 ,  C25B11/075 ,  B01J37/16 ,  C01G3/00 ,  C07C1/12 ,  C22B15/00 ,  C30B7/14 ,  C30B29/02 ,  C30B29/64

CPC分类号： H10B69/00 ,  B01J37/16 ,  C01G3/00 ,  C07C1/12 ,  C22B15/00 ,  C25B3/25 ,  C25B11/051 ,  C25B11/075 ,  C30B7/14 ,  C30B29/02 ,  C30B29/64 ,  G11C16/04 ,  H01L23/528 ,  H10B41/27 ,  H10B41/30 ,  H10B43/00 ,  H10B43/20 ,  H10B43/30 ,  C07C2523/72

摘要： A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

公开(公告)号：US20230240069A1

公开(公告)日：2023-07-27

申请号：US18157828

申请日：2023-01-22

申请人： SK hynix Inc.

发明人： Sung Lae OH ,  Sang Hyun SUNG ,  Hyun Soo SHIN

IPC分类号： H10B43/20 ,  H10B43/10

CPC分类号： H10B43/20 ,  H10B43/10

摘要： A memory device may include an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers that are alternately stacked on a substrate; a trench in the electrode structure, and having an upper sidewall, a lower sidewall and a horizontal portion that couples the upper sidewall to the lower sidewall and that is parallel to a top surface of the substrate; a dielectric layer in the trench; and a slimming hole in the electrode structure having a sidewall of the trench and a region of the dielectric layer, and having a bottom surface disposed on an electrode layer on which the horizontal portion of the trench is positioned.

公开(公告)号：US20230230920A1

公开(公告)日：2023-07-20

申请号：US18192322

申请日：2023-03-29

申请人： SK hynix Inc.

发明人： Dong Hyuk KIM ,  Sung Lae OH ,  Tae Sung PARK ,  Soo Nam JUNG

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/535 ,  G11C7/18 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L23/535 ,  G11C7/18 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

摘要： A semiconductor device includes a first connection pattern; a bit line disposed over the first connection pattern in a vertical direction; and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern, and formed as an island when viewed along the vertical direction. A predetermined number of the bit-line contact pads are spaced apart from each other by a predetermined distance in a first direction, when viewed along the vertical direction.

公开(公告)号：US11700730B2

公开(公告)日：2023-07-11

申请号：US17129146

申请日：2020-12-21

申请人： Micron Technology, Inc.

发明人： Sanh D. Tang ,  John K. Zahurak

IPC分类号： H01L27/11582 ,  H01L27/11551 ,  H10B43/27 ,  H01L21/28 ,  H01L27/06 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H10B41/10 ,  H10B41/20 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H10B63/00 ,  H01L21/768 ,  G11C13/00 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L23/528 ,  H10N70/20

CPC分类号： H10B43/27 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/76838 ,  H01L23/528 ,  H01L27/0688 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/10 ,  H10B41/20 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H10B63/34 ,  H10B63/845 ,  G11C2213/71 ,  H10N70/231

摘要： Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

公开(公告)号：US11677021B2

公开(公告)日：2023-06-13

申请号：US18092727

申请日：2023-01-03

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach

IPC分类号： H01L29/78 ,  G11C16/02 ,  G11C11/404 ,  G11C11/4097 ,  H10B10/00 ,  H10B12/00 ,  H10B43/20 ,  H10B69/00 ,  H10B63/00 ,  G11C11/412 ,  G11C16/04

CPC分类号： H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C16/02 ,  H01L29/7841 ,  H10B10/12 ,  H10B12/20 ,  H10B43/20 ,  H10B63/30 ,  H10B69/00 ,  G11C11/412 ,  G11C16/0483 ,  G11C2213/71

摘要： A semiconductor device, the device comprising: a first silicon layer comprising first single crystal silicon; an isolation layer disposed over said first silicon layer; a first metal layer disposed over said isolation layer; a second metal layer disposed over said first metal layer; a first level comprising a plurality of transistors, said first level disposed over said second metal layer, wherein said isolation layer comprises an oxide to oxide bond surface, wherein said plurality of transistors comprise a second single crystal silicon region; and a plurality of capacitors, wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.