公开(公告)号：US20140306343A1

公开(公告)日：2014-10-16

申请号：US14251470

申请日：2014-04-11

Applicant: XINTEC INC.

Inventor： Yu-Lung HUANG ,  Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/78

CPC classification number: H01L24/14 ,  H01L21/78 ,  H01L22/12 ,  H01L22/20 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14131 ,  H01L2224/14145 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/14146 ,  H01L2224/81 ,  H01L2224/81907 ,  H01L2924/00012 ,  H01L2224/11

Abstract: A chip package is provided, in which includes: a packaging substrate, a chip and a plurality solder balls interposed between the packaging substrate and the chip for bonding the packaging substrate and the chip, wherein the solder balls include a first portion of a first size and a second portion of a second size that is different from the first size.

Abstract translation: 提供了一种芯片封装，其中包括：封装基板，芯片和介于封装基板和芯片之间的多个焊球，用于接合封装基板和芯片，其中焊球包括第一尺寸的第一部分 以及与第一尺寸不同的第二尺寸的第二部分。

公开(公告)号：US20140284792A1

公开(公告)日：2014-09-25

申请号：US14298436

申请日：2014-06-06

Applicant: XINTEC INC.

Inventor： Wei-Ming CHEN ,  Shu-Ming CHANG

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24246 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/83

Abstract: A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.

Abstract translation: 公开了一种芯片封装。 封装包括载体衬底，至少两个半导体芯片，填充材料层，保护层和多个导电凸块。 载体基板包括接地区域。 半导体芯片设置在载体基板的接地区域上。 每个半导体芯片包括至少一个信号焊盘，并且包括电连接到接地区域的至少一个接地焊盘。 填充材料层形成在载体衬底上并覆盖半导体芯片。 保护层覆盖填充层。 多个导电凸块设置在保护层的上方并与半导体芯片电连接。 还公开了芯片封装的制造方法。

公开(公告)号：US20140252659A1

公开(公告)日：2014-09-11

申请号：US14199640

申请日：2014-03-06

Applicant: XINTEC INC.

Inventor： Yung-Tai TSAI ,  Shu-Ming CHANG ,  Chun-Wei CHANG ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L2224/02371 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00014

Abstract: A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad.

Abstract translation: 半导体结构包括晶片，至少一个非金属氧化物层，焊盘，钝化层，隔离层和导电层。 晶片具有连接在第二和第三表面之间的第一表面，第二表面，第三表面，第一阶段差异表面以及连接在第一和第三表面之间的第二阶段差异表面。 非金属氧化物层位于晶片的第一表面上。 垫位于非金属氧化物层上并电连接到晶片。 钝化层位于非金属氧化物层上。 隔离层位于钝化层，非金属氧化物层，晶片的第一，第二和第三表面以及晶片的第一和第二级差分表面上。 导电层位于隔离层上并电接触焊盘。

公开(公告)号：US20140231966A1

公开(公告)日：2014-08-21

申请号：US14260205

申请日：2014-04-23

Applicant: XINTEC INC.

Inventor： Bai-Yao LOU ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Tzu-Hsiang HUNG

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/73153 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括具有第一表面和第二表面的基板; 位于所述第一表面上的导电垫结构; 位于所述基板的所述第一表面上的电介质层和所述导电焊盘结构，其中所述电介质层具有暴露所述导电焊盘结构的一部分的开口; 以及位于电介质层上并填充到开口中的盖层。

公开(公告)号：US20140203387A1

公开(公告)日：2014-07-24

申请号：US14157379

申请日：2014-01-16

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Yen-Shih HO ,  Tsang-Yu LIU

IPC: H01L31/02

CPC classification number: H01L31/02005 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/525 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/11472 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2224/0231 ,  H01L2224/11

Abstract: Disclosed herein is a semiconductor chip package, which includes a semiconductor chip, a plurality of vias, an isolation layer, a redistribution layer, and a packaging layer. The vias extend from the lower surface to the upper surface of the semiconductor chip. The vias include at least one first via and at least one second via. The isolation layer also extends from the lower surface to the upper surface of the semiconductor chip, and part of the isolation layer is disposed in the vias. The sidewall of the first via is totally covered by the isolation layer while the sidewall of the second via is partially covered by the isolation layer. The redistribution layer is disposed below the isolation layer and fills the plurality of vias, and the packaging layer is disposed below the isolation layer.

Abstract translation: 这里公开了一种半导体芯片封装，其包括半导体芯片，多个通孔，隔离层，再分布层和封装层。 通孔从半导体芯片的下表面延伸到上表面。 通孔包括至少一个第一通孔和至少一个第二通孔。 隔离层也从半导体芯片的下表面延伸到上表面，并且隔离层的一部分设置在通孔中。 第一通孔的侧壁完全被隔离层覆盖，而第二通孔的侧壁被隔离层部分地覆盖。 再分配层设置在隔离层下方并填充多个通孔，并且包装层设置在隔离层下方。

公开(公告)号：US20140199835A1

公开(公告)日：2014-07-17

申请号：US14214389

申请日：2014-03-14

Applicant: XINTEC INC.

Inventor： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Long-Sheng YEOU

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/13025 ,  H01L2224/9202 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein an upper sidewall of the hole inclines to the lower surface of the substrate, and a lower sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

Abstract translation: 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电垫; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的上侧壁倾斜到所述衬底的下表面，并且所述孔的下侧壁或底部暴露所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。

公开(公告)号：US20140191350A1

公开(公告)日：2014-07-10

申请号：US14150637

申请日：2014-01-08

Applicant: XINTEC INC.

Inventor： Chih-Hao CHEN ,  Bai-Yao LOU ,  Shih-Kuang CHEN

IPC: H01L31/0232 ,  H01L27/146

CPC classification number: H01L27/14687 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14698 ,  H01L2224/13

Abstract: An image sensor chip package is disclosed, which includes a substrate, an image sensor component formed on the substrate, a spacer formed on the substrate and surrounding the image sensor component, and a transparent plate. A stress notch is formed on a side of the transparent plate, and a breaking surface is extended from the stress notch. A method for fabricating the image sensor chip package is also disclosed.

Abstract translation: 公开了一种图像传感器芯片封装，其包括基板，形成在基板上的图像传感器部件，形成在基板上并围绕图像传感器部件的间隔件和透明板。 在透明板的一侧形成有应力缺口，并且断裂面从应力凹口延伸。 还公开了一种用于制造图像传感器芯片封装的方法。

公开(公告)号：US08766431B2

公开(公告)日：2014-07-01

申请号：US13828537

申请日：2013-03-14

Applicant: Xintec Inc.

Inventor： Baw-Ching Perng ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Ji Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

IPC: H01L23/04

CPC classification number: H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

Abstract translation: 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

公开(公告)号：US08722463B2

公开(公告)日：2014-05-13

申请号：US13734796

申请日：2013-01-04

Applicant: Xintec Inc.

Inventor： Chien-Hung Liu

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3512 ,  H01L2924/00

Abstract: The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region.

Abstract translation: 本发明涉及一种芯片封装，其包括：具有至少一个焊盘区域和至少一个器件区域的半导体衬底，其中半导体衬底在焊盘区域中包括多个重掺杂区域，以及两个重掺杂 区域绝对隔离; 设置在所述焊盘区域上方的多个导电焊盘结构; 设置在所述芯片封装的侧壁处的至少一个开口以暴露所述重掺杂区域; 以及设置在所述开口中以与所述重掺杂区域电接触的导电图案。

公开(公告)号：US08716109B2

公开(公告)日：2014-05-06

申请号：US14030058

申请日：2013-09-18

Applicant: Xintec Inc.

Inventor： Ching-Yu Ni ,  Chang-Sheng Hsu

IPC: H01L21/00

CPC classification number: H01L21/78 ,  B81B7/0051 ,  B81C2203/0118 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/585 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/93 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/16 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/2732 ,  H01L2224/27618 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/95001 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages.

Abstract translation: 根据本发明的实施例提供了芯片封装及其制造方法。 芯片封装包含具有芯片的半导体衬底。 封装层设置在半导体衬底上。 间隔件设置在半导体衬底和封装层之间，其中由半导体衬底，间隔件和封装层组成的侧表面具有凹部。 该方法包括在半导体晶片的多个芯片和封装层之间形成多个间隔物，其中对应于每个芯片的每个间隔件彼此分离，并且间隔件从芯片的边缘向内收缩以形成凹部 并且沿着任何两个相邻芯片之间的划线切割半导体晶片以形成多个芯片封装。