公开(公告)号：US20080100986A1

公开(公告)日：2008-05-01

申请号：US11907563

申请日：2007-10-15

Applicant: Seung Hyun Sohn ,  Yul Kyo Chung ,  Sung Taek Lim ,  Hyung Mi Jung

Inventor： Seung Hyun Sohn ,  Yul Kyo Chung ,  Sung Taek Lim ,  Hyung Mi Jung

IPC: H01G4/00 ,  H01L21/20

CPC classification number: H01G4/33 ,  H01G4/228 ,  H05K1/162 ,  H05K3/388 ,  H05K3/4069 ,  H05K3/4652 ,  H05K2201/0179 ,  H05K2201/035 ,  H05K2201/09509 ,  H05K2201/09763

Abstract: Provided is a method of manufacturing a capacitor embedded printed circuit board. In the method, a laminated body is prepared, including a laminated plate having first and second copper films on both sides thereof, where at least one bottom electrode is provided on at least one side. A dielectric layer is formed on the at least one bottom electrode. A metal layer is formed on a top surface of the dielectric layer where a capacitor is to be formed. A conductive paste layer is formed on at least one region of a top surface of the metal layer, where the conductive paste layer and the metal layer is provided as a top electrode. An insulation resin layers are formed on both sides of the laminated plate, respectively. A conductive via is formed in the insulation resin layer such that it is connected to the conductive paste layer.

Abstract translation: 提供一种制造电容器嵌入式印刷电路板的方法。 在该方法中，制备层压体，其包括其两侧具有第一和第二铜膜的层压板，其中在至少一侧上设置有至少一个底部电极。 在所述至少一个底部电极上形成介电层。 在要形成电容器的电介质层的顶表面上形成金属层。 在金属层的顶表面的至少一个区域上形成导电浆料层，其中导电浆料层和金属层设置为顶部电极。 绝缘树脂层分别形成在层压板的两侧。 导电通孔形成在绝缘树脂层中，使其与导电糊层连接。

公开(公告)号：US20080099539A1

公开(公告)日：2008-05-01

申请号：US11975227

申请日：2007-10-17

Applicant: Cheng Tay ,  Pek Tan ,  Swee Cheng ,  Eng Yap

Inventor： Cheng Tay ,  Pek Tan ,  Swee Cheng ,  Eng Yap

IPC: B23K31/02 ,  B23K37/00

CPC classification number: B23K1/0016 ,  B23K2101/42 ,  H01L21/4853 ,  H01L21/486 ,  H05K3/3484 ,  H05K2201/0266 ,  H05K2201/035 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2203/043 ,  H05K2203/1476

Abstract: In one embodiment, a method is provided. The method comprises filling a microvia formed in a bond pad with solder paste comprising solder balls of the first size; and coating the bond pad with solder paste comprising solder balls of the second size, wherein the second size is greater than the first size.

Abstract translation: 在一个实施例中，提供了一种方法。 该方法包括用形成第一尺寸的焊球的焊膏填充在焊盘中形成的微孔; 以及用包括第二尺寸的焊球的焊膏涂覆所述接合焊盘，其中所述第二尺寸大于所述第一尺寸。

公开(公告)号：US20080099230A1

公开(公告)日：2008-05-01

申请号：US11927144

申请日：2007-10-29

Applicant: Michimasa TAKAHASHI ,  Masakazu Aoyama

Inventor： Michimasa TAKAHASHI ,  Masakazu Aoyama

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/00

CPC classification number: H05K3/4691 ,  H05K1/0218 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4664 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/096 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A flex-rigid wiring board includes a flexible board including a flexible substrate and a conductor pattern formed over the flexible substrate, a non-flexible substrate disposed adjacent to the flexible board, an insulating layer including an inorganic material and covering the flexible board and the non-flexible substrate, the insulating layer exposing at least one portion of the flexible board, a conductor pattern formed on the insulating layer, and a plating layer connecting the conductor pattern of the flexible board and the conductor pattern on the insulating layer.

Abstract translation: 弹性刚性布线板包括柔性基板，该柔性基板包括柔性基板和形成在柔性基板上的导体图案，邻近柔性基板设置的非柔性基板，包括无机材料并覆盖柔性基板的绝缘层和 非柔性基板，绝缘层暴露柔性板的至少一部分，形成在绝缘层上的导体图案，以及将柔性基板的导体图案与导体图案连接在绝缘层上的镀层。

公开(公告)号：US07365435B2

公开(公告)日：2008-04-29

申请号：US11200044

申请日：2005-08-10

Applicant: Paul James Brown

Inventor： Paul James Brown

IPC: H01L23/48

CPC classification number: H05K1/114 ,  H01L21/50 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K3/429 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/097 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A printed circuit board (PCB) assembly having a plurality of circuit layers including outer layers and intervening layers with through-vias and micro-vias used to translate a portion of the signal connections of the grid, thereby creating a set of diagonal routing channels between the vias on internal layers of the board and a BGA package mounted on the printed circuit board.

Abstract translation: 一种具有多个电路层的印刷电路板（PCB）组件，其包括外层和具有通孔和微通孔的中间层，其用于平移网格的信号连接的一部分，由此产生一组对角线路由信道， 板上内部的通孔和安装在印刷电路板上的BGA封装。

公开(公告)号：US20080087986A1

公开(公告)日：2008-04-17

申请号：US11986998

申请日：2007-11-27

Applicant: Ravindra Tanikella

Inventor： Ravindra Tanikella

IPC: H01L23/532 ,  H01L23/52

CPC classification number: H01L23/49894 ,  C08F283/04 ,  C08G73/121 ,  C08K3/36 ,  C08K9/10 ,  C08K2201/011 ,  C08L79/08 ,  C08L2666/66 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15791 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/28 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/1163 ,  H05K2203/121 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.

Abstract translation: 用于微电子封装的高度可靠的互连。 在一个实施例中，积聚互连中的电介质层具有玻璃化转变温度的等级; 并且稍后施加的电介质层在低于较早施加的电介质层的玻璃化转变温度的温度下被层压。 在一个实施方案中，通过热固化工艺增加了积聚互连中早期施加的介电膜的玻璃化转变温度，以超过用于层压后来施加的电介质膜的温度。 在一个实施方案中，在层压聚酰亚胺材料的膜（例如，通过催化剂的密封剂的光化学或热降解）之后，用嵌入的催化剂形成聚酰亚胺材料以促进交联。 在一个实施例中，阻焊剂开口壁具有通过激光辅助接种产生的可湿性层，使得阻焊剂开口壁之间没有间隙，并且在阻焊剂开口中没有底部填充物。

公开(公告)号：US20080079140A1

公开(公告)日：2008-04-03

申请号：US11868919

申请日：2007-10-08

Applicant: Peter Salmon

Inventor： Peter Salmon

IPC: H01L23/50 ,  H05K1/16

CPC classification number: H05K3/363 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05573 ,  H01L2224/11332 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/81052 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3651 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4015 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0568 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/05599

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server or supercomputer embodiment is also described.

Abstract translation: 本说明书描述了用于制造电子系统模块的技术。 该模块包括具有窄至5微米或更小的迹线宽度的柔性多层互连电路。 与用于制造液晶显示器，LCD，面板的玻璃面板制造设备相似，优选地用于制造互连电路。 使用剥离层在玻璃面板上制造多层互连电路。 在互连电路上形成特殊的组装层，该电路包括在输入/输出（I / O）焊盘位置处形成有开口的厚电介质层。 使用刮刀将焊膏沉积在开口中以形成填充有焊料的孔。 IC芯片在I / O焊盘位置处设有金柱凸起，并且这些凸块插入孔中以形成倒装芯片连接。 IC芯片经过测试和返工。 相同的凹凸/连接可用于连接细间距电缆。 提供模块封装层用于密封和电磁屏蔽。 还描述了刀片服务器或超级计算机实施例。

公开(公告)号：US20080073110A1

公开(公告)日：2008-03-27

申请号：US11902251

申请日：2007-09-20

Applicant: Takeshi Shioga ,  Kazuaki Kurihara ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi

Inventor： Takeshi Shioga ,  Kazuaki Kurihara ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H05K1/162 ,  H01L21/486 ,  H01L23/15 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/4605 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10378 ,  Y10T29/49002 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The interposer includes a glass substrate 46 with first through-electrodes 47 buried in; a plurality of resin layers 68, 20, 32 supported by the glass substrate; thin film capacitors 18a, 18b buried between a first resin layer 68 of the plural resin layers and a second resin layer 20 of the plural resin layers and including the first capacitor electrodes 12a, 12b, the second capacitor electrodes 16 opposed to the first capacitor electrodes 12a, 12b, and a dielectric thin film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and the second through-electrodes 77a, 77b penetrating the plural resin layers 68, 20, 32, electrically connected to the first through-electrode 47 and electrically connected to the first capacitor electrode 12a, 12b or the second capacitor electrode 16.

Abstract translation: 插入件包括：第一贯通电极47被埋入的玻璃基板46; 由玻璃基板支撑的多个树脂层68,20,32; 埋在多个树脂层的第一树脂层68和多个树脂层的第二树脂层20之间并且包括第一电容器电极12a，12b的第二电容器电极16的薄膜电容器18a，18b， 形成在第一电容器电极12 a，12 b和第二电容器电极16之间的相对介电常数为200或更大的第一电容器电极12a，12b和电介质薄膜14，以及第二贯通电极77 a，77b穿透电连接到第一通孔47并与第一电容器电极12a，2b或第二电容器电极16电连接的多个树脂层68,20,32。

公开(公告)号：US20080060840A1

公开(公告)日：2008-03-13

申请号：US11832892

申请日：2007-08-02

Applicant: Youhong WU

Inventor： Youhong WU

IPC: H01R12/06 ,  H05K3/46

CPC classification number: H05K1/115 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  Y10T29/49165

Abstract: A multi-layer printed wiring board has a core substrate, a throughhole structure, a first interlayer insulation layer, a first via, a second interlayer insulation layer and a second via. The core substrate has a throughhole opening, and the throughhole structure is formed in the throughhole opening. The first interlayer insulation layer is formed over the core substrate. The first via is formed in the first interlayer insulation layer and has a bottom portion having a first radius. The second interlayer insulation layer is formed over the first interlayer insulation layer and the first via. The second via is formed in the second interlayer insulation layer and has a bottom portion having a second radius greater than the first radius. The first via is positioned inside a circle having a radius (D1) from a gravity center of the throughhole opening, and the radius (D1) of the circle satisfies a formula, (D1)=(R)+(r)/3, where (R) represents a radius of the throughhole opening and (r) represents the first radius of the first via.

Abstract translation: 多层印刷电路板具有核心基板，通孔结构，第一层间绝缘层，第一通孔，第二层间绝缘层和第二通孔。 核心基板具有通孔开口，并且通孔结构形成在通孔开口中。 在芯基板上形成第一层间绝缘层。 第一通孔形成在第一层间绝缘层中，并且具有第一半径的底部。 第二层间绝缘层形成在第一层间绝缘层和第一通孔之上。 第二通孔形成在第二层间绝缘层中，并且具有大于第一半径的第二半径的底部。 第一通孔位于从通孔开口重心的半径（D1）的圆内，圆的半径（D1）满足式（D1）=（R）+（r）/ 3， 其中（R）表示通孔开口的半径，（r）表示第一通孔的第一半径。

公开(公告)号：US07328506B2

公开(公告)日：2008-02-12

申请号：US10281463

申请日：2002-10-25

Applicant: Miguel A. Jimarez ,  Ross W. Keesler ,  Voya R. Markovich ,  Rajinder S. Rai ,  Cheryl L. Tytran-Palomaki

Inventor： Miguel A. Jimarez ,  Ross W. Keesler ,  Voya R. Markovich ,  Rajinder S. Rai ,  Cheryl L. Tytran-Palomaki

IPC: H01K3/10

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/3484 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09863 ,  H05K2203/043 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for forming a plated microvia interconnect. An external dielectric layer (EDL) is mounted on a surface of the substrate and is in direct mechanical contact with a conductive element included in the surface. An opening formed in the EDL exposes the conductive element and creates a microvia in the EDL. A sidewall and bottom wall surface of the microvia is treated to promote copper adhesion to the sidewall and bottom wall surfaces. The sidewall and bottom wall surfaces are plated to form a layer of copper thereon. The layer of copper is in direct mechanical and electrical contact with the conductive element. A wet solder paste deposited on the layer of copper overfills a remaining portion of the microvia. The solder paste is reflowed to form a solder bump in and over the remaining portion of the microvia to form the plated microvia interconnect.

Abstract translation: 一种形成电镀微孔互连的方法。 外部电介质层（EDL）安装在基板的表面上，并且与包括在表面中的导电元件直接机械接触。 EDL中形成的开口露出导电元件，并在EDL中产生微孔。 处理微孔的侧壁和底壁表面以促进铜附着到侧壁和底壁表面。 侧壁和底壁表面被电镀以在其上形成一层铜层。 铜层与导电元件直接机械和电接触。 沉积在铜层上的湿焊膏过量填充微孔的剩余部分。 焊膏被回流以在微孔的剩余部分中和上方形成焊料凸块以形成电镀微孔互连。

公开(公告)号：US20080030965A1

公开(公告)日：2008-02-07

申请号：US11701441

申请日：2007-02-02

Applicant: Chung-Cheng Lien ,  Chih-Kui Yang

Inventor： Chung-Cheng Lien ,  Chih-Kui Yang

IPC: H05K1/00

CPC classification number: H05K1/162 ,  H05K3/4602 ,  H05K2201/0355 ,  H05K2201/09509 ,  Y10T29/49126

Abstract: A circuit board structure with capacitor embedded therein and method for fabricating the same are disclosed, especially a core structure with capacitors embedded therein and method for fabricating the same. The structure comprising: a core board having a dielectric layer with a first surface and an opposite second surface; at least one high dielectric coefficient material layer formed in the dielectric layer, wherein a first electrode plate formed on the other surface of the high dielectric coefficient material layer; a first circuit layer formed on the first surface of the dielectric layer; a second circuit layer formed on the second surface of the dielectric layer and having a second electrode plate corresponding to the first electrode plate; and a first conductive via formed in the dielectric layer and electrically connecting the first electrode plate and the first circuit layer.

Abstract translation: 公开了一种其中嵌有电容器的电路板结构及其制造方法，特别是其中嵌有电容器的芯结构及其制造方法。 该结构包括：芯板，具有具有第一表面和相对的第二表面的电介质层; 形成在所述电介质层中的至少一个高介电系数材料层，其中形成在所述高介电系数材料层的另一个表面上的第一电极板; 形成在所述电介质层的第一表面上的第一电路层; 形成在电介质层的第二表面上并具有与第一电极板对应的第二电极板的第二电路层; 以及形成在电介质层中并电连接第一电极板和第一电路层的第一导电通孔。