公开(公告)号：US6106891A

公开(公告)日：2000-08-22

申请号：US215992

申请日：1998-12-18

申请人： Joseph Duane Kulesza ,  Voya Rista Markovich ,  Kostas Papathomas ,  Joseph Gene Sabia

发明人： Joseph Duane Kulesza ,  Voya Rista Markovich ,  Kostas Papathomas ,  Joseph Gene Sabia

IPC分类号： B32B7/04 ,  C08G59/40 ,  C08G73/00 ,  C08L63/00 ,  C09D163/00 ,  H01B1/20 ,  H01B1/22 ,  H01B1/24 ,  H05K1/09 ,  H05K1/11 ,  H05K1/16 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

CPC分类号： H01B1/24 ,  B32B7/04 ,  H01B1/22 ,  H05K1/095 ,  H05K1/113 ,  H05K1/167 ,  H05K3/4053 ,  H05K3/4069 ,  H01L2224/16235 ,  H05K1/16 ,  H05K2201/0347 ,  H05K2201/09563 ,  H05K2201/10734 ,  H05K2203/0126 ,  H05K2203/0191 ,  H05K2203/0207 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0763 ,  H05K3/0023 ,  H05K3/0047 ,  H05K3/0094 ,  Y10S428/901 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24273 ,  Y10T428/24331 ,  Y10T428/24339 ,  Y10T428/24826 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/25

摘要： The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.

摘要翻译： 本发明允许焊接接头直接制成通孔和通孔，而不会通过用环氧树脂或氰酸盐填充组合物填充电镀通孔，焊料不会被弄脏到通孔或通孔中。 当固化和过度镀覆时，填充组合物为焊接接头提供支撑，并为相互连接提供平坦的可焊接表面。 在某些实施方案中，固化的填充组合物提供另外的导电性的优点。 本发明还涉及用这种填充组合物填充通孔的几种新方法，以及位于通孔和通孔中的电阻器。

公开(公告)号：US5940729A

公开(公告)日：1999-08-17

申请号：US633984

申请日：1996-04-17

申请人： Francis Joseph Downes, Jr. ,  Stephen Joseph Fuerniss ,  Gary Ray Hill ,  Anthony Paul Ingraham ,  Voya Rista Markovich ,  Jaynal Abedin Molla

发明人： Francis Joseph Downes, Jr. ,  Stephen Joseph Fuerniss ,  Gary Ray Hill ,  Anthony Paul Ingraham ,  Voya Rista Markovich ,  Jaynal Abedin Molla

IPC分类号： H01L21/60 ,  H01L23/13 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H05K3/34 ,  H05K3/46 ,  H01L21/44

CPC分类号： H01L23/49833 ,  H01L23/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/81052 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/15787 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/0023 ,  H05K3/3436 ,  H05K3/4644

摘要： According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.

公开(公告)号：US5659256A

公开(公告)日：1997-08-19

申请号：US601923

申请日：1996-02-15

申请人： Richard Gordon Charlton ,  George Charles Correia ,  Mark Andrew Couture ,  Gary Ray Hill ,  Kibby Barth Horsford ,  Anthony Paul Ingraham ,  Michael David Lowell ,  Voya Rista Markovich ,  Gordon Charles Osborne, Jr. ,  Mark Vincent Pierson

发明人： Richard Gordon Charlton ,  George Charles Correia ,  Mark Andrew Couture ,  Gary Ray Hill ,  Kibby Barth Horsford ,  Anthony Paul Ingraham ,  Michael David Lowell ,  Voya Rista Markovich ,  Gordon Charles Osborne, Jr. ,  Mark Vincent Pierson

IPC分类号： G01R1/04 ,  G01R1/073 ,  G01R31/28

CPC分类号： G01R1/0483 ,  G01R1/07307 ,  G01R31/2863 ,  G01R31/2886

摘要： A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

公开(公告)号：US6150255A

公开(公告)日：2000-11-21

申请号：US373868

申请日：1999-08-13

申请人： Francis Joseph Downes, Jr. ,  Stephen Joseph Fuerniss ,  Gary Ray Hill ,  Anthony Paul Ingraham ,  Voya Rista Markovich ,  Jaynal Abedin Molla

发明人： Francis Joseph Downes, Jr. ,  Stephen Joseph Fuerniss ,  Gary Ray Hill ,  Anthony Paul Ingraham ,  Voya Rista Markovich ,  Jaynal Abedin Molla

IPC分类号： H01L21/60 ,  H01L23/13 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H05K3/34 ,  H05K3/46 ,  H01L21/44

CPC分类号： H01L23/49833 ,  H01L23/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/81052 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/15787 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/0023 ,  H05K3/3436 ,  H05K3/4644

摘要： According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.

摘要翻译： 根据本发明，提供了一种用于为平坦化基板提供焊球，特别是多层陶瓷基板的树枝状连接的技术。 在衬底在顶表面上具有凸起的中心部分的情况下，其上设置有顶表面冶金衬垫，一层适形的可光成像材料放置在顶表面上。 可光成像材料以对应于顶表面冶金垫的图案的图案曝光和显影，以在可光成像材料中形成通孔。 将铜镀在与顶部表面冶金垫接触的通孔中。 然后将光致变形表面的暴露表面平坦化，优选通过机械抛光以形成平坦的平坦表面，其中通孔的端部暴露。 然后，树枝状连接器焊盘在I / C芯片的焊球连接可释放地连接到的通孔的暴露端上生长。

公开(公告)号：US6138350A

公开(公告)日：2000-10-31

申请号：US30587

申请日：1998-02-25

申请人： Anilkumar Chinuprasad Bhatt ,  Donald Herman Glatzel ,  Allen F. Moring ,  Voya Rista Markovich ,  Kostas Papathomas ,  David John Russell

发明人： Anilkumar Chinuprasad Bhatt ,  Donald Herman Glatzel ,  Allen F. Moring ,  Voya Rista Markovich ,  Kostas Papathomas ,  David John Russell

IPC分类号： H05K1/11 ,  H05K3/00 ,  H05K3/02 ,  H05K3/24 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H01K3/10

CPC分类号： H05K3/4652 ,  H05K1/113 ,  H05K3/4069 ,  H05K3/4602 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/12044 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/092 ,  H05K2201/0959 ,  H05K2203/0191 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0554 ,  H05K3/0023 ,  H05K3/0094 ,  H05K3/025 ,  H05K3/246 ,  H05K3/429 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/24942 ,  Y10T428/249996

摘要： A process for manufacturing circuit boards comprising providing a circuitized substrate having a dielectric surface, providing a peel apart structure including a metal layer and a peelable film, laminating the peel apart structure to the circuitized substrate with the metal layer positioned adjacent said dielectric surface, forming holes in the circuitized substrate through the peel apart structure, applying a filler material including an organic base to the peel apart structure, applying a sacrificial film onto the filler material, and applying sufficient heat and pressure to the sacrificial film to force the filler material into the holes to substantially fill the holes is provided.

摘要翻译： 一种用于制造电路板的方法，包括提供具有电介质表面的电路化基板，提供包括金属层和可剥离膜的剥离结构，将剥离结构层压到电路化基板上，金属层位于邻近所述电介质表面，形成 通过剥离结构在电路化基板中的孔，将包含有机基底的填充材料施加到剥离结构上，将牺牲膜施加到填充材料上，以及向牺牲膜施加足够的热和压力以迫使填充材料进入 提供基本上填充孔的孔。

公开(公告)号：US6027858A

公开(公告)日：2000-02-22

申请号：US870950

申请日：1997-06-06

申请人： Gerald Walter Jones ,  Ross William Keesler ,  Voya Rista Markovich ,  Heinke Marcello ,  James Warren Wilson ,  William Earl Wilson

发明人： Gerald Walter Jones ,  Ross William Keesler ,  Voya Rista Markovich ,  Heinke Marcello ,  James Warren Wilson ,  William Earl Wilson

IPC分类号： G03F7/038 ,  G03F7/16 ,  H05K3/00 ,  H05K3/46 ,  G03C11/12 ,  G03F7/00

CPC分类号： H05K3/0094 ,  G03F7/0385 ,  G03F7/161 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2203/066 ,  H05K2203/1394 ,  H05K3/0023

摘要： A process of tenting plated through holes with a photoimageable dielectric is provided which includes a dielectric film comprising a photoimageable epoxy based resin layer and a peelable polyester layer. In accordance with the process of the present invention, the peelable polyester layer of the dielectric film is removed prior to baking, developing, patterning or curing the structure.

摘要翻译： 提供了一种用可光成像的电介质通孔穿孔的方法，其包括包括可光成像的环氧树脂层和可剥离聚酯层的电介质膜。 根据本发明的方法，在烘烤，显影，图案化或固化该结构之前去除电介质膜的可剥离聚酯层。

公开(公告)号：US5981880A

公开(公告)日：1999-11-09

申请号：US699902

申请日：1996-08-20

申请人： Bernd Karl-Heinz Appelt ,  Anilkumar Chinuprasad Bhatt ,  James W. Fuller, Jr. ,  John Matthew Lauffer ,  Voya Rista Markovich ,  William John Rudik ,  William Earl Wilson

发明人： Bernd Karl-Heinz Appelt ,  Anilkumar Chinuprasad Bhatt ,  James W. Fuller, Jr. ,  John Matthew Lauffer ,  Voya Rista Markovich ,  William John Rudik ,  William Earl Wilson

IPC分类号： H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H05K1/03 ,  H05K3/42 ,  H05K3/46 ,  H05K1/00

CPC分类号： H01L23/564 ,  H01L21/481 ,  H01L23/498 ,  H01L23/49894 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/036 ,  H05K1/0366 ,  H05K2201/0195 ,  H05K2201/0769 ,  H05K2201/09718 ,  H05K2201/09881

摘要： A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.

摘要翻译： 用于诸如球栅阵列封装或有机芯片载体封装的电子器件封装中的印刷电路板包括用于分离和绝缘电源芯的无玻璃电介质，电路或电镀通孔，以防止由 导电材料沿着玻璃基预浸料衬底的迁移。

公开(公告)号：US5893983A

公开(公告)日：1999-04-13

申请号：US758272

申请日：1996-11-19

申请人： John Joseph Konrad ,  Voya Rista Markovich ,  George Frederick Reel ,  Jose Antonio Rios ,  Timothy Leroy Wells ,  Michael Wozniak

发明人： John Joseph Konrad ,  Voya Rista Markovich ,  George Frederick Reel ,  Jose Antonio Rios ,  Timothy Leroy Wells ,  Michael Wozniak

IPC分类号： B24B7/06 ,  B24B37/04 ,  B24B41/047 ,  C23F1/08 ,  H05K3/06 ,  H05K3/26 ,  C23F1/02 ,  C23F1/44

CPC分类号： C23F1/08 ,  B24B37/04 ,  B24B41/047 ,  B24B7/06 ,  H05K3/068 ,  H05K3/26 ,  H05K2203/025 ,  H05K2203/0346 ,  H05K2203/0353 ,  H05K2203/1509

摘要： A technique for polishing an exposed surface of metal on a substrate to remove defects from mechanical working of metals, such as burrs and pigtails resulting from drilling, and defects from plating, such as nodules and depressions, is provided. The substrate has an exposed metal surface such as copper thereon which is to be treated to remove defects. A planarizing or polishing head, preferably a rotating roller, is provided which is continuously rotating with respect to the substrate, with the head in contact with the metal surface on the substrate. A chemical etchant, essentially free of abrasive material, is continuously supplied to the interface between the metal surface and the head. The treating and polishing continues until the defects have been removed or reduced to an acceptable value. In some instances where significant height reduction is required, thus requiring significant metal removal, several passes of the substrate may be required or a device with multiple heads may be used. The polishing head preferably includes a film having a layer of very fine grit embedded therein, such as 5.mu.-15.mu. silicon carbide (SiC).

摘要翻译： 提供了用于抛光基板上的金属暴露表面以去除金属机械加工的缺陷的技术，例如钻孔引起的毛刺和辫子以及电镀缺陷，例如结节和凹陷。 基板具有暴露的金属表面，例如铜，其被处理以去除缺陷。 提供平面化或抛光头，优选为旋转辊，其相对于衬底连续旋转，头部与衬底上的金属表面接触。 基本上不含研磨材料的化学蚀刻剂被连续供应到金属表面和头部之间的界面。 继续进行处理和抛光，直到缺陷被去除或降低到可接受的值。 在需要显着降低高度的一些情况下，因此需要显着的金属去除，可能需要多次通过基底，或者可以使用具有多个头部的装置。 抛光头优选包括具有嵌入其中的非常细的砂粒层的膜，例如5-15微米的碳化硅（SiC）。

公开(公告)号：US5817405A

公开(公告)日：1998-10-06

申请号：US795180

申请日：1997-02-04

申请人： Anikumar Chinuprasad Bhatt ,  Ashwinkumar Chinuprasad Bhatt ,  Robert Jeffrey Day ,  Thomas Patrick Duffy ,  Jeffrey Alan Knight ,  Richard William Malek ,  Voya Rista Markovich

发明人： Anikumar Chinuprasad Bhatt ,  Ashwinkumar Chinuprasad Bhatt ,  Robert Jeffrey Day ,  Thomas Patrick Duffy ,  Jeffrey Alan Knight ,  Richard William Malek ,  Voya Rista Markovich

IPC分类号： H05K1/02 ,  H05K3/06 ,  H05K3/10 ,  H05K3/42 ,  B32B9/00

CPC分类号： H05K1/0265 ,  H05K3/108 ,  H05K3/428 ,  H05K1/0263 ,  H05K2201/0347 ,  H05K2201/09727 ,  H05K2203/0353 ,  H05K2203/072 ,  H05K2203/1407 ,  H05K3/064 ,  Y10S428/901 ,  Y10T428/24322 ,  Y10T428/24917

摘要： A process for making a circuitized substrate is defined wherein the substrate is treated with two different, e.g., additive and subtractive, metallization processes. The process is thus able to effectively produce substrates including conductive features, e. g., high density circuit lines and chip heat-sinking pads, of two different degrees of resolution in a cost effective and expeditious manner. The resulting product is also defined.

摘要翻译： 定义制造电路化衬底的方法，其中用两种不同的，例如添加和减去的金属化工艺处理衬底。 因此，该方法能够有效地产生包括导电特征的基底， 例如，高密度电路线和芯片散热垫，具有两种不同程度的分辨率，具有成本效益和快速的方式。 所得产品也被定义。

公开(公告)号：US5707893A

公开(公告)日：1998-01-13

申请号：US566363

申请日：1995-12-01

申请人： Anilkumar Chinuprasad Bhatt ,  Ashwinkumar Chinuprasad Bhatt ,  Robert Jeffrey Day ,  Thomas Patrick Duffy ,  Jeffrey Alan Knight ,  Richard William Malek ,  Voya Rista Markovich

发明人： Anilkumar Chinuprasad Bhatt ,  Ashwinkumar Chinuprasad Bhatt ,  Robert Jeffrey Day ,  Thomas Patrick Duffy ,  Jeffrey Alan Knight ,  Richard William Malek ,  Voya Rista Markovich

IPC分类号： H05K1/02 ,  H05K3/06 ,  H05K3/10 ,  H05K3/42 ,  H01L21/445

CPC分类号： H05K1/0265 ,  H05K3/108 ,  H05K3/428 ,  H05K1/0263 ,  H05K2201/0347 ,  H05K2201/09727 ,  H05K2203/0353 ,  H05K2203/072 ,  H05K2203/1407 ,  H05K3/064 ,  Y10S428/901 ,  Y10T428/24322 ,  Y10T428/24917

摘要： A process for making a circuitized substrate is defined wherein the substrate is treated with two different, e.g., additive and subtractive, metallization processes. The process is thus able to effectively produce substrates including conductive features, e.g., high density circuit lines and chip heat-sinking pads, of two different degrees of resolution in a cost effective and expeditious manner. The resulting product is also defined.

摘要翻译： 定义制造电路化衬底的方法，其中用两种不同的，例如添加和减去的金属化工艺处理衬底。 因此，该方法能够以成本有效和快速的方式有效地产生包括两种不同分辨率度的导电特征（例如，高密度电路线和芯片散热垫）的衬底。 所得产品也被定义。