公开(公告)号：US10083912B2

公开(公告)日：2018-09-25

申请号：US15041026

申请日：2016-02-10

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Zhiwei Gong ,  Wei Gao

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06582 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85

摘要： A package substrate having an opening and through-substrate interconnect structures is attached to a temporary carrier such as an adhesive film. The active surface of an IC die is placed in contact with the carrier substrate within the opening, to temporarily attach the die to the carrier substrate. Another die is attached to the side of the first die furthest from the carrier substrate. In one embodiment, the dies are attached to each other using an epoxy so that their respective non-active surfaces face each other. Bond wires are connected between interconnects at the active surface of the second die and the substrate. The wires are then encapsulated. After removal of the carrier substrate, a build-up interconnect structure is formed that includes external interconnects of the package substrate, such as solder balls of a ball grid array package.

公开(公告)号：US10068821B2

公开(公告)日：2018-09-04

申请号：US13944837

申请日：2013-07-17

申请人： NICHIA CORPORATION

发明人： Takeaki Shirase ,  Toru Hashimoto

IPC分类号： H01L23/06 ,  H01L23/13 ,  H01L23/495 ,  H01L23/00 ,  H01L23/29 ,  H01L33/62

CPC分类号： H01L23/13 ,  H01L23/293 ,  H01L23/49503 ,  H01L23/49513 ,  H01L24/32 ,  H01L33/62 ,  H01L2224/04026 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29118 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/293 ,  H01L2224/32014 ,  H01L2224/32056 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48666 ,  H01L2224/48669 ,  H01L2224/48684 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83138 ,  H01L2224/83143 ,  H01L2224/83385 ,  H01L2224/83424 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83473 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2924/01322 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/15151 ,  H01L2924/15156 ,  H01L2924/15165 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/3025 ,  H01L2924/3641 ,  H01L2924/3656 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor component support is provided which includes a component support portion for a semiconductor component to be mounted on the semiconductor component support portion. The component support portion includes a metal part that includes an opening in plan view. The opening of the metal part includes first and second sections. The second section communicates with the first section, and is arranged outside the first section. The second section is wider than the first section. The first section can be at least partially positioned directly under a mount-side main surface of the semiconductor component.

公开(公告)号：US10037900B1

公开(公告)日：2018-07-31

申请号：US15590757

申请日：2017-05-09

申请人： NXP B.V.

发明人： Ernst Seler ,  Jorn Isaksen ,  Shamsuddin Ahmed ,  Ralf Reuter

IPC分类号： H01L23/02 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/50 ,  H01L23/00

CPC分类号： H01L21/563 ,  H01L23/13 ,  H01L23/3178 ,  H01L24/16 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/15151

摘要： A device is disclosed. The device includes a baseboard including a first set of metallic contact pads, a semiconductor integrated chip (IC) package including a second set of metallic contact pads and metallic interconnects to connect the first set of metallic contacts pads and the second set of metallic contact pads through metallic interconnects. The second set of metallic contact pads includes a first group of contact pads and a second group of contact pads. The first group of contact pads are designed to carry a high frequency signal. The baseboard includes a plurality of holes that at least partially segregates a first group of metallic interconnects that connects the first group of contact pads to the baseboard and a second group of metallic interconnects that connects the second group of contact pads to the baseboard.

公开(公告)号：US20180197840A1

公开(公告)日：2018-07-12

申请号：US15915769

申请日：2018-03-08

申请人： INTEL CORPORATION

发明人： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/49 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L25/07

CPC分类号： H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49 ,  H01L23/528 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/96 ,  H01L25/07 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06575 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US20180175113A1

公开(公告)日：2018-06-21

申请号：US15824858

申请日：2017-11-28

申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

发明人： Akira FURUYA ,  Koichi KOYAMA ,  Mitsuharu HIRANO

IPC分类号： H01L27/30 ,  H01L21/48 ,  H01L21/67

CPC分类号： H01L27/304 ,  G02B6/30 ,  H01L21/486 ,  H01L21/67236 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/10 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/42 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/014

摘要： A semiconductor device includes: a printed substrate having a through hole from an upper face to a lower face thereof; a first semiconductor element mounted on the printed substrate; an interposer mounted on the upper face of the printed substrate; a second semiconductor element adjacent to the interposer and arranged to overlap with the through hole; and a bonding wire coupling a first pad to a second pad, the first pad being on an upper face of the interposer and being positioned on the second semiconductor element side, the second pad being on an upper face of the second semiconductor element and being positioned on the interposer side, wherein the interposer has an edge face protruding with respect to a wall face of the through hole of the printed substrate toward the second semiconductor element, and the edge face faces with an edge face of the second semiconductor element.

公开(公告)号：US20180175089A1

公开(公告)日：2018-06-21

申请号：US15547254

申请日：2016-02-02

申请人： SONY CORPORATION

发明人： YUSUKE MADA

IPC分类号： H01L27/146 ,  G02B7/02 ,  H04N5/225 ,  H04N5/369

CPC分类号： H01L27/14618 ,  G02B7/02 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L27/14 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/83139 ,  H01L2224/83194 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/92225 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/16151 ,  H01L2924/16152 ,  H04N5/2251 ,  H04N5/2253 ,  H04N5/2257 ,  H04N5/369 ,  H01L2224/45099 ,  H01L2224/13099

摘要： The present technology relates to a camera module and an electronic apparatus that can lower the risk of breakage. An imaging element has a light receiving surface to receive light, and is flip-chip mounted on a base. A joining material is joined to the optical back surface of the imaging element so that a space is formed between the joining material and a back-surface-side member provided on the side of the optical back surface on the opposite side of the imaging element from the light receiving surface. The present technology can be applied to camera modules and the like that capture images, for example.

公开(公告)号：US09985007B2

公开(公告)日：2018-05-29

申请号：US15393083

申请日：2016-12-28

申请人： Invensas Corporation

发明人： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC分类号： H01L23/10 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

摘要： Package-on-package (“PoP”) devices with multiple levels and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. First and second conductive lines are coupled to the upper surface of the package substrate respectively at different heights in a fan-out region. A first molding layer is formed over the upper surface of the package substrate. A first and a second wafer-level packaged microelectronic component are located above an upper surface of the first molding layer respectively surface mount coupled to a first and a second set of upper portions of the first conductive lines. A third and a fourth wafer-level packaged microelectronic component are located above the first and the second wafer-level packaged microelectronic component respectively surface mount coupled to a first and a second set of upper portions of the second conductive lines.

公开(公告)号：US09972609B2

公开(公告)日：2018-05-15

申请号：US15393112

申请日：2016-12-28

申请人： Invensas Corporation

发明人： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC分类号： H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

摘要： Package-on-package (“PoP”) devices with WLP (“WLP”) components with dual RDLs (“RDLs”) for surface mount dies and methods therefor. In a PoP, a first IC die surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located between a first RDL and a second RDL. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components.

公开(公告)号：US09972601B2

公开(公告)日：2018-05-15

申请号：US14768209

申请日：2014-09-26

申请人： INTEL CORPORATION

发明人： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC分类号： H01L25/065 ,  H01L23/49 ,  H01L25/07 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49 ,  H01L23/528 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/96 ,  H01L25/07 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/207

摘要： Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US09972573B2

公开(公告)日：2018-05-15

申请号：US15393048

申请日：2016-12-28

申请人： Invensas Corporation

发明人： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

摘要： Wafer-level packaged components are disclosed. In a wafer-level-packaged, an integrated circuit die has first contacts in an inner third region of a surface of the integrated circuit die. A redistribution layer has second contacts in an inner third region of a first surface of the redistribution layer and third contacts in an outer third region of a second surface of the redistribution layer opposite the first surface thereof. The second contacts of the redistribution layer are coupled for electrical conductivity to the first contacts of the integrated circuit die with the surface of the integrated circuit die face-to-face with the first surface of the redistribution layer. The third contacts are offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the redistribution layer, the third contacts being surface mount contacts.