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公开(公告)号:US20180102331A1
公开(公告)日:2018-04-12
申请号:US15830745
申请日:2017-12-04
Applicant: Invensas Corporation
Inventor: Cyprian Emeka Uzoh
IPC: H01L23/00 , H01L21/768 , H01L23/48 , H01L25/00
CPC classification number: H01L24/02 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L25/00 , H01L2224/02166 , H01L2224/02372 , H01L2224/05548 , H01L2224/11 , H01L2224/11011 , H01L2224/13024 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , Y10T29/49165 , H01L2924/00
Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.
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公开(公告)号:US20170309518A1
公开(公告)日:2017-10-26
申请号:US15649457
申请日:2017-07-13
Applicant: Invensas Corporation
Inventor: Cyprian Emeka Uzoh , Guilian Gao , Liang Wang , Hong Shen , Arkalgud R. Sitaram
Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.
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公开(公告)号:US09780042B2
公开(公告)日:2017-10-03
申请号:US15171604
申请日:2016-06-02
Applicant: Invensas Corporation
Inventor: Charles G. Woychik , Cyprian Emeka Uzoh , Hiroaki Sato
IPC: H01L23/58 , H01L23/00 , H01L23/48 , H01L21/768 , H01L23/498 , H01L25/065 , H01L21/48 , H01L23/433 , H01L25/16 , H01L25/18
CPC classification number: H01L23/562 , H01L21/4857 , H01L21/486 , H01L21/76898 , H01L23/4334 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L24/03 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/167 , H01L25/18 , H01L2224/0401 , H01L2224/131 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/48227 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06589 , H01L2924/00014 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/157 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/19105 , H01L2924/19106 , H01L2924/3011 , H01L2924/014 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a thickness of 200 microns or less, and can have a plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness. The support element can have a body of at least one of dielectric or semiconductor material exposed at a second surface of the support element, openings extending through a thickness of the body, conductive vias extending within at least some of the openings in a direction of the thickness of the body, and terminals exposed at a first surface of the support element. The second surface of the support element can be united with the second surface of the substrate element. The terminals can be electrically connected with the contacts through the conductive vias and the electrically conductive structure.
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公开(公告)号:US09769923B2
公开(公告)日:2017-09-19
申请号:US15380172
申请日:2016-12-15
Applicant: Invensas Corporation
Inventor: Bong-Sub Lee , Cyprian Emeka Uzoh , Charles G. Woychik , Liang Wang , Laura Wills Mirkarimi , Arkalgud R. Sitaram
IPC: H05K13/04 , H05K1/09 , H01L23/498 , H01L21/48 , H05K1/11
CPC classification number: H05K1/097 , H01L21/4857 , H01L21/486 , H01L21/4867 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L2224/16225 , H01L2924/0002 , H01L2924/15192 , H01L2924/15311 , H05K1/112 , H05K1/113 , H05K1/165 , H05K3/188 , Y10T29/49117 , Y10T29/49124 , Y10T29/5313 , H01L2924/00
Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.
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公开(公告)号:US09728527B2
公开(公告)日:2017-08-08
申请号:US14925807
申请日:2015-10-28
Applicant: Invensas Corporation
Inventor: Cyprian Emeka Uzoh , Rajesh Katkar
IPC: H01L23/48 , H01L25/00 , H01L23/538 , H01L23/00 , H01L23/498 , H01L21/48 , H01L25/065 , H01L21/311 , H01L21/56 , H01L21/768
CPC classification number: H01L25/50 , H01L21/31111 , H01L21/4853 , H01L21/563 , H01L21/76898 , H01L23/49811 , H01L23/5384 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/24 , H01L24/32 , H01L24/33 , H01L24/43 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/89 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L2224/02311 , H01L2224/02317 , H01L2224/02371 , H01L2224/02372 , H01L2224/0239 , H01L2224/0331 , H01L2224/0332 , H01L2224/0333 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/03614 , H01L2224/0391 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/04042 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05169 , H01L2224/05184 , H01L2224/05547 , H01L2224/05565 , H01L2224/05568 , H01L2224/05569 , H01L2224/05611 , H01L2224/05616 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/05684 , H01L2224/08146 , H01L2224/0823 , H01L2224/1134 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11903 , H01L2224/1191 , H01L2224/13022 , H01L2224/13023 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/13184 , H01L2224/13565 , H01L2224/13616 , H01L2224/1403 , H01L2224/14131 , H01L2224/14134 , H01L2224/16145 , H01L2224/16146 , H01L2224/16148 , H01L2224/16227 , H01L2224/17181 , H01L2224/24147 , H01L2224/24227 , H01L2224/244 , H01L2224/32145 , H01L2224/32225 , H01L2224/3303 , H01L2224/33181 , H01L2224/45015 , H01L2224/45147 , H01L2224/45565 , H01L2224/4805 , H01L2224/48108 , H01L2224/48149 , H01L2224/4903 , H01L2224/49426 , H01L2224/73201 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81192 , H01L2224/81193 , H01L2224/81825 , H01L2224/94 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06524 , H01L2225/06548 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/16152 , H01L2924/16251 , H01L2924/181 , H01L2924/19107 , H01L2924/381 , H01L2924/3841 , H01L2924/386 , H01L2924/00 , H01L2924/01029 , H01L2924/014 , H01L2924/00012 , H01L2924/01074 , H01L2924/01028 , H01L2924/01082 , H01L2224/05 , H01L2224/13 , H01L2224/16225 , H01L2224/81 , H01L2224/45616 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2224/45099
Abstract: An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.
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公开(公告)号:US20170207159A1
公开(公告)日:2017-07-20
申请号:US15477265
申请日:2017-04-03
Applicant: Invensas Corporation
Inventor: Rajesh Katkar , Cyprian Emeka Uzoh , Belgacem Haba , Ilyas Mohammed
IPC: H01L23/498 , H01L21/48 , H01L23/538 , H01L23/373 , H01L23/00 , H01L25/065
CPC classification number: H05K1/0306 , H01L21/481 , H01L21/4853 , H01L21/486 , H01L23/13 , H01L23/3731 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/49894 , H01L23/5381 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L24/17 , H01L25/0655 , H01L25/0657 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2225/06517 , H01L2225/0652 , H01L2225/06548 , H01L2225/06572 , H01L2225/06586 , H01L2225/06589 , H01L2225/1023 , H01L2225/107 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H05K1/09 , H05K1/112 , H05K1/115 , H05K3/4007 , H05K3/42 , H05K2201/09545 , H05K2201/10378 , H05K2203/0323
Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.
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公开(公告)号:US20170186801A1
公开(公告)日:2017-06-29
申请号:US15461001
申请日:2017-03-16
Applicant: Invensas Corporation
Inventor: Cyprian Emeka Uzoh , Rajesh Katkar
IPC: H01L27/146
CPC classification number: H01L27/14634 , H01L21/568 , H01L23/3114 , H01L24/09 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/46 , H01L24/48 , H01L24/49 , H01L24/82 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L27/14618 , H01L27/14636 , H01L2224/04042 , H01L2224/04105 , H01L2224/09181 , H01L2224/32145 , H01L2224/32225 , H01L2224/48101 , H01L2224/48227 , H01L2224/4903 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2225/06506 , H01L2225/0651 , H01L2924/00014 , H01L2924/143 , H01L2924/19104 , H01L2924/19105 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
Abstract: In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/−10 degrees.
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公开(公告)号:US20170117243A1
公开(公告)日:2017-04-27
申请号:US15332533
申请日:2016-10-24
Applicant: Invensas Corporation
Inventor: Rajesh Katkar , Gabriel Z. Guevara , Xuan Li , Cyprian Emeka Uzoh , Guilian Gao , Liang Wang
CPC classification number: H01L24/16 , H01L21/565 , H01L23/315 , H01L24/27 , H01L24/32 , H01L24/49 , H01L24/81 , H01L24/85 , H01L25/105 , H01L25/50 , H01L2224/13109 , H01L2224/13111 , H01L2224/1319 , H01L2224/16111 , H01L2224/16227 , H01L2224/32225 , H01L2224/45015 , H01L2224/45147 , H01L2224/48227 , H01L2224/85355 , H01L2225/1023 , H01L2225/1058 , H01L2225/1082 , H01L2924/15311 , H01L2924/19107 , H01L2924/00014 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755
Abstract: A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the wire bonds.
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公开(公告)号:US20170099733A1
公开(公告)日:2017-04-06
申请号:US15380172
申请日:2016-12-15
Applicant: Invensas Corporation
Inventor: Bong-Sub Lee , Cyprian Emeka Uzoh , Charles G. Woychik , Liang Wang , Laura Wills Mirkarimi , Arkalgud R. Sitaram
IPC: H05K1/09 , H01L21/48 , H05K1/11 , H01L23/498
CPC classification number: H05K1/097 , H01L21/4857 , H01L21/486 , H01L21/4867 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L2224/16225 , H01L2924/0002 , H01L2924/15192 , H01L2924/15311 , H05K1/112 , H05K1/113 , H05K1/165 , H05K3/188 , Y10T29/49117 , Y10T29/49124 , Y10T29/5313 , H01L2924/00
Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.
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公开(公告)号:US09601467B1
公开(公告)日:2017-03-21
申请号:US14845150
申请日:2015-09-03
Applicant: Invensas Corporation
Inventor: Cyprian Emeka Uzoh , Rajesh Katkar
IPC: H01L23/48 , H01L23/52 , H01L25/065 , H01L23/00 , H01L23/31
CPC classification number: H01L27/14634 , H01L21/568 , H01L23/3114 , H01L24/09 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/46 , H01L24/48 , H01L24/49 , H01L24/82 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L27/14618 , H01L27/14636 , H01L2224/04042 , H01L2224/04105 , H01L2224/09181 , H01L2224/32145 , H01L2224/32225 , H01L2224/48101 , H01L2224/48227 , H01L2224/4903 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2225/06506 , H01L2225/0651 , H01L2924/00014 , H01L2924/143 , H01L2924/19104 , H01L2924/19105 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
Abstract: In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/−10 degrees.
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