公开(公告)号：US20150228628A1

公开(公告)日：2015-08-13

申请号：US14694811

申请日：2015-04-23

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.

Abstract translation: 半导体器件具有形成在半导体管芯的第一表面上的第一导热层。 半导体管芯的第二表面安装到牺牲载体上。 密封剂沉积在第一导热层和牺牲载体上。 将密封剂平坦化以暴露第一导热层。 第一绝缘层形成在半导体管芯的第二表面和密封剂的第一表面上。 半导体管芯的第二表面上的第一绝缘层的一部分被去除。 在第一绝缘层的去除部分内的半导体管芯的第二表面上形成第二导热层。 在第二导热层周围的绝缘层内形成导电层。 散热器可以安装在第一导热层上。

公开(公告)号：US09076655B2

公开(公告)日：2015-07-07

申请号：US13743054

申请日：2013-01-16

Applicant: STATS ChipPAC, Ltd.

Inventor： Duk Ju Na ,  Calvert Tan ,  Chang Beom Yong

IPC: H01L21/44 ,  H01L21/02

CPC classification number: H01L21/02697 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05666 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/92222 ,  H01L2224/92242 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/04941 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2221/68304 ,  H01L2224/27 ,  H01L2221/68372 ,  H01L21/56 ,  H01L2221/68381 ,  H01L21/563 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor device can be formed by first providing a semiconductor wafer, and forming a conductive via into the semiconductor wafer. A portion of the semiconductor wafer can be removed so that the conductive via extends above a surface of the semiconductor wafer. A first insulating layer can be formed over the surface of the semiconductor wafer and the conductive via, followed by a second insulating layer, the second insulating layer having a different material composition than the first insulating layer. Portions of the insulating layers can be removed to expose the conductive via.

Abstract translation: 可以通过首先提供半导体晶片并在半导体晶片中形成导电通孔来形成半导体器件。 可以去除半导体晶片的一部分，使得导电通孔延伸到半导体晶片的表面之上。 可以在半导体晶片和导电通孔的表面上形成第一绝缘层，随后是第二绝缘层，第二绝缘层具有与第一绝缘层不同的材料组成。 可以去除部分绝缘层以露出导电通孔。

公开(公告)号：US20150179616A1

公开(公告)日：2015-06-25

申请号：US14624136

申请日：2015-02-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/568 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/82

Abstract: A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices.

Abstract translation: 半导体器件具有形成在衬底上的第一构建互连结构。 第一构建互连结构包括绝缘层和形成在绝缘层上的导电层。 垂直互连结构和半导体管芯设置在第一堆积互连结构之上。 半导体管芯，第一堆叠互连结构和衬底设置在载体上。 密封剂沉积在半导体管芯，第一堆积互连结构和衬底上。 第二堆积互连结构形成在密封剂上。 第二堆叠互连结构通过垂直互连结构电连接到第一堆叠互连结构。 衬底提供结构支撑并防止形成第一和第二堆积互连结构期间的翘曲。 在形成第二堆积互连结构之后去除衬底。 绝缘层的一部分被去除，暴露出导电层用于随后堆叠的半导体器件的电互连。

公开(公告)号：US09064936B2

公开(公告)日：2015-06-23

申请号：US13832333

申请日：2013-03-15

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Seung Wook Yoon

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L21/683 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/03 ,  H01L2224/03002 ,  H01L2224/03003 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0613 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2224/82005 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

Abstract translation: 半导体器件具有沉积在半导体管芯的第一表面上并且围绕半导体管芯的密封剂。 在半导体管芯的与第一表面相对的第二表面上形成第一绝缘层。 导电层形成在第一绝缘层上。 通过半导体管芯的覆盖区外的密封剂形成互连结构，并电连接到导电层。 第一绝缘层包括光学透明或半透明材料。 半导体管芯包括被配置为接收穿过第一绝缘层的外部刺激的传感器。 在半导体管芯的第一表面上形成第二绝缘层。 通过半导体管芯的覆盖区外的第一绝缘层形成导电通孔。 多个层叠的半导体器件通过互连结构电连接。

公开(公告)号：US09059186B2

公开(公告)日：2015-06-16

申请号：US14154049

申请日：2014-01-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC: H01L21/4763 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each including a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.

Abstract translation: 嵌入式半导体管芯封装通过使用粘合剂将框架载体安装到临时载体上而制成。 框架载体包括每个包括围绕腔的引线框架互连结构的管芯安装位置。 半导体管芯设置在每个腔中。 将密封剂沉积在模具上的空腔中。 封装互连结构形成在引线框架互连结构和密封剂上。 封装互连结构和引线框互连结构电连接到管芯。 帧载体被分成单独的嵌入式芯片封装。 半导体管芯可以垂直堆叠或并排放置在腔内。 嵌入式管芯封装可以通过引线框互连结构堆叠并电互连。 半导体器件可以安装到嵌入式裸片封装并且通过引线框互连结构电连接到裸片。

公开(公告)号：US20150145126A1

公开(公告)日：2015-05-28

申请号：US14564427

申请日：2014-12-09

Applicant: STATS CHIPPAC, LTD.

Inventor： Yaojian Lin ,  II Kwon Shim ,  Seng Guan Chow

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer.

Abstract translation: 半导体器件具有在指定用于凸块形成的位置中安装到临时衬底的应力释放缓冲器。 应力消除缓冲器可以是多层复合材料，例如第一顺应层，在第一柔性层上形成的硅层，以及形成在硅层上的第二柔性层。 半导体管芯也安装在临时衬底上。 应力消除缓冲器可以比半导体管芯更薄。 密封剂沉积在半导体管芯和应力释放缓冲器之间。 移除临时衬底。 在半导体管芯，密封剂和应力释放缓冲器上形成互连结构。 互连结构电连接到半导体管芯。 可以在应力消除缓冲器和密封剂上形成加强层。 可以在应力消除缓冲器内形成包含有源器件，无源器件，导电层和电介质层的电路层。

公开(公告)号：US20150137334A1

公开(公告)日：2015-05-21

申请号：US14600825

申请日：2015-01-20

Applicant: STATS ChipPAC, Ltd.

Inventor： SinJae Lee ,  JinGwan Kim ,  JiHoon Oh ,  JaeHyun Lim ,  KyuWon Lee

IPC: H01L25/065 ,  H01L23/552 ,  H01L21/768 ,  H01L21/56 ,  H01L23/48 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15156 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die.

Abstract translation: 半导体器件具有互连结构，其中腔部分地穿过互连结构形成。 第一半导体管芯安装在空腔中。 通过第一半导体管芯形成第一TSV。 在互连结构和第一半导体管芯上沉积粘合剂层。 屏蔽层安装在第一半导体管芯上。 屏蔽层通过粘合剂层固定到第一半导体管芯，并通过第一TSV和互连结构接地以阻止电磁干扰。 第二半导体管芯安装到屏蔽层并电连接到互连结构。 通过第二半导体管芯形成第二TSV。 密封剂沉积在屏蔽层，第二半导体管芯和互连结构之上。 通过屏蔽层形成狭缝以使密封剂流入空腔并覆盖第一半导体管芯。

公开(公告)号：US20150115465A1

公开(公告)日：2015-04-30

申请号：US14329464

申请日：2014-07-11

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Hin Hwa Goh ,  Il Kwon Shim

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/485 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24155 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/82

Abstract: A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

Abstract translation: 半导体器件具有基板。 通过衬底形成导电通孔。 在衬底的第一表面上形成多个第一接触焊盘。 在衬底的第二表面上形成多个第二接触焊盘。 在衬底的第二表面上形成虚拟图案。 在衬底的侧壁中形成凹陷。 通过基板形成开口。 密封剂沉积在开口中。 在衬底的第二表面上形成绝缘层。 在绝缘层中形成有虚设的开口。 半导体管芯与衬底相邻地设置。 密封剂沉积在半导体管芯和衬底上。 衬底的第一表面包括大于衬底的第二表面的宽度的宽度。

公开(公告)号：US08980691B2

公开(公告)日：2015-03-17

申请号：US13931397

申请日：2013-06-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/24 ,  H01L23/02 ,  H01L23/52 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device includes a substrate having an insulating layer and a conductive layer embedded in the insulating layer. The conductive layer is patterned to form conductive pads or conductive pillars. The substrate includes a first encapsulant formed over the conductive layer. A first opening is formed through insulating layer and first encapsulant using a stamping process or laser direct ablation. The substrate is separated into individual units, which are mounted to a carrier. A semiconductor die is disposed in the first opening in the substrate. A second encapsulant is deposited over the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and substrate. An opening is formed through the second encapsulant and through the insulating layer to expose the conductive layer. A bump is formed in the second opening over the conductive layer outside a footprint of the semiconductor die.

Abstract translation: 半导体器件包括具有绝缘层和嵌入绝缘层中的导电层的衬底。 将导电层图案化以形成导电焊盘或导电柱。 衬底包括形成在导电层上的第一密封剂。 通过使用冲压工艺或激光直接烧蚀的绝缘层和第一密封剂形成第一开口。 将基板分离成单独的单元，其安装到载体上。 半导体管芯设置在衬底的第一开口中。 第二密封剂沉积在半导体管芯和衬底上。 在半导体管芯和衬底上形成互连结构。 通过第二密封剂形成开口并穿过绝缘层以露出导电层。 在半导体管芯的覆盖区外的导电层上的第二开口中形成凸块。

公开(公告)号：US08975980B2

公开(公告)日：2015-03-10

申请号：US14018282

申请日：2013-09-04

Applicant: STATS ChipPAC, Ltd.

Inventor： Kai Liu ,  Robert C. Frye ,  Yaojian Lin

IPC: H01P3/08 ,  H01F19/00 ,  H03H7/42 ,  H03H7/09 ,  H03H7/01 ,  H01L49/02

CPC classification number: H03H7/422 ,  H01L28/10 ,  H03H7/09 ,  H03H7/1766 ,  H03H7/42

Abstract: A band-pass filter has a plurality of frequency band channels each including a first inductor having a first terminal coupled to a first balanced port and a second terminal coupled to a second balanced port. A first capacitor is coupled between the first and second terminals of the first inductor. A second inductor has a first terminal coupled to a first unbalanced port and a second terminal coupled to a second unbalanced port. The second inductor is disposed within a first distance of the first inductor to induce magnetic coupling. A second capacitor is coupled between the first and second terminals of the second inductor. A third inductor is disposed within a second distance of the first inductor and within a third distance of the second inductor to induce magnetic coupling. A second capacitor is coupled between first and second terminals of the third inductor.

Abstract translation: 带通滤波器具有多个频带信道，每个频带信道包括具有耦合到第一平衡端口的第一端子的第一电感器和耦合到第二平衡端口的第二端子。 第一电容器耦合在第一电感器的第一和第二端子之间。 第二电感器具有耦合到第一不平衡端口的第一端子和耦合到第二不平衡端口的第二端子。 第二电感器设置在第一电感器的第一距离内以引起磁耦合。 第二电容器耦合在第二电感器的第一和第二端子之间。 第三电感器设置在第一电感器的第二距离内并且在第二电感器的第三距离内，以引起磁耦合。 第二电容器耦合在第三电感器的第一和第二端子之间。