公开(公告)号：US20090085227A1

公开(公告)日：2009-04-02

申请号：US11914581

申请日：2006-05-09

Applicant: Tsukasa Shiraishi ,  Seiichi Nakatani ,  Seiji Karashima ,  Koichi Hirano ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu

Inventor： Tsukasa Shiraishi ,  Seiichi Nakatani ,  Seiji Karashima ,  Koichi Hirano ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L21/563 ,  H01L23/552 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/83007 ,  H01L2224/83051 ,  H01L2224/83101 ,  H01L2224/83136 ,  H01L2224/83139 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/83888 ,  H01L2224/9201 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/303 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10568 ,  H05K2201/10977 ,  H05K2201/2036 ,  H05K2203/083 ,  H05K2203/087 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/13111

Abstract: A flip chip mounting body in which a circuit substrate having a plurality of connection terminals and an electronic part (semiconductor chip) having a plurality of electrode terminals are aligned face to face with each other, with a resin composition composed of solder powder, a resin and a convection additive being sandwiched in between, while a means such as spacers is interposed in between so as to provide a uniform gap between the two parts, or the electronic part (semiconductor chip) is placed inside a plate-shaped member having two or more protruding portions, so that the solder powder is allowed to move through boiling of the convection additive and to be self-aggregated to form a solder layer, thereby electrically connecting the connection terminals and the electrode terminals; and a mounting method for such a mounting body.

Abstract translation: 一种倒装芯片安装体，其中具有多个连接端子的电路基板和具有多个电极端子的电子部件（半导体芯片）彼此面对面地对准，其中树脂组合物由焊料粉末，树脂 并且夹在其间的对流添加剂，同时诸如间隔物的装置插入其间，以便在两个部件之间提供均匀的间隙，或者将电子部件（半导体芯片）放置在具有两个或 更多的突出部分，使得焊料粉末能够通过对流添加剂的沸腾而移动并且自聚集形成焊料层，从而电连接连接端子和电极端子; 以及这种安装体的安装方法。

公开(公告)号：US20080210458A1

公开(公告)日：2008-09-04

申请号：US11976848

申请日：2007-10-29

Applicant: Yoshihisa Yamashita ,  Toshio Fujii ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Satoru Tomekawa ,  Hiroki Yabe

Inventor： Yoshihisa Yamashita ,  Toshio Fujii ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Satoru Tomekawa ,  Hiroki Yabe

IPC: H05K1/03

CPC classification number: H05K3/386 ,  H01L51/424 ,  H01L2924/0002 ,  H05K1/16 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4614 ,  H05K2201/0191 ,  H05K2201/0376 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A flexible substrate comprises: (i) a film; (ii) an insulating resin layer formed on each of a front face of the film and a rear face of the film, which rear face is opposite to the front face; (iii) a front-sided wiring pattern embedded in the insulating resin layer formed on the front face of the film, and a rear-sided wiring pattern embedded in the insulating resin layer formed on the rear face of the film; and (iv) a via which is located between the front-sided wiring pattern and the rear-sided wiring pattern and serves to electrically interconnect the front-sided wiring pattern and the rear-sided wiring pattern, wherein the insulating resin layer formed on each of the front face and the rear face of the film is thicker than the film.

Abstract translation: 柔性基板包括：（i）膜; （ii）形成在所述膜的前表面和所述膜的后表面中的每一个上的绝缘树脂层，所述后表面与所述前表面相对; （iii）嵌入到形成在所述膜前表面上的所述绝缘树脂层中的正面布线图案和嵌入在所述膜背面形成的所述绝缘树脂层中的背面布线图案; 以及（iv）位于前侧布线图案和背面布线图案之间的通孔，用于将前侧布线图案和背面布线图案电连接，其中形成在每个布线图案上的绝缘树脂层 的膜的前表面和后表面比膜厚。

公开(公告)号：US20080047137A1

公开(公告)日：2008-02-28

申请号：US11826758

申请日：2007-07-18

Applicant: Toshiyuki Asahi ,  Seiji Karashima ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Tousaku Nishiyama ,  Koichi Hirano ,  Osamu Shibata ,  Takeshi Nakayama ,  Yoshiyuki Saito

Inventor： Toshiyuki Asahi ,  Seiji Karashima ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Tousaku Nishiyama ,  Koichi Hirano ,  Osamu Shibata ,  Takeshi Nakayama ,  Yoshiyuki Saito

IPC: H01R43/20 ,  H01R12/00 ,  H01R13/24

CPC classification number: H05K3/403 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H01R13/2414 ,  H05K1/0218 ,  H05K1/0284 ,  H05K1/141 ,  H05K1/145 ,  H05K1/182 ,  H05K3/20 ,  H05K3/3442 ,  H05K3/361 ,  H05K3/366 ,  H05K3/368 ,  H05K2201/043 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/055 ,  H05K2201/056 ,  H05K2201/09036 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2203/302 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49208 ,  H01L2924/00

Abstract: A connection member can be produced without a via-forming step. The connection member includes an insulating substrate which has an upper surface, a lower surface opposed to the upper surface, and a side surface which connects these surfaces; and at least one wiring which extends from the upper surface to the lower surface through the side surface.

Abstract translation: 可以在没有通孔形成步骤的情况下制造连接构件。 连接构件包括绝缘基板，其具有上表面，与上表面相对的下表面和连接这些表面的侧表面; 以及至少一个通过侧面从上表面延伸到下表面的布线。

公开(公告)号：US07258549B2

公开(公告)日：2007-08-21

申请号：US11060550

申请日：2005-02-18

Applicant: Toshiyuki Asahi ,  Seiji Karashima ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Tousaku Nishiyama ,  Koichi Hirano ,  Osamu Shibata ,  Takeshi Nakayama ,  Yoshiyuki Saito

Inventor： Toshiyuki Asahi ,  Seiji Karashima ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Tousaku Nishiyama ,  Koichi Hirano ,  Osamu Shibata ,  Takeshi Nakayama ,  Yoshiyuki Saito

IPC: H01R12/00

CPC classification number: H05K3/403 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H01R13/2414 ,  H05K1/0218 ,  H05K1/0284 ,  H05K1/141 ,  H05K1/145 ,  H05K1/182 ,  H05K3/20 ,  H05K3/3442 ,  H05K3/361 ,  H05K3/366 ,  H05K3/368 ,  H05K2201/043 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/055 ,  H05K2201/056 ,  H05K2201/09036 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2203/302 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49208 ,  H01L2924/00

Abstract: A connection member can be produced without a via-forming step. The connection member includes an insulating substrate which has an upper surface, a lower surface opposed to the upper surface, and a side surface which connects these surfaces; and at least one wiring which extends from the upper surface to the lower surface through the side surface.

Abstract translation: 可以在没有通孔形成步骤的情况下制造连接构件。 连接构件包括绝缘基板，其具有上表面，与上表面相对的下表面和连接这些表面的侧表面; 以及至少一个通过侧面从上表面延伸到下表面的布线。

公开(公告)号：US20070151756A1

公开(公告)日：2007-07-05

申请号：US11712943

申请日：2007-03-02

Applicant: Yoshihisa Yamashita ,  Hiroki Yabe ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Satoru Tomekawa ,  Toshio Fujii ,  Seiji Karashima

Inventor： Yoshihisa Yamashita ,  Hiroki Yabe ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Satoru Tomekawa ,  Toshio Fujii ,  Seiji Karashima

IPC: H05K1/16

CPC classification number: H05K3/4084 ,  G03G15/225 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K1/0393 ,  H05K3/102 ,  H05K3/1266 ,  H05K3/20 ,  H05K3/207 ,  H05K3/386 ,  H05K3/4652 ,  H05K2201/0376 ,  H05K2203/0143 ,  H05K2203/0195 ,  H05K2203/0517 ,  H05K2203/1189 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A flexible substrate comprises a film, a first insulating resin layer on a front face of the film, a second insulating resin layer on a rear face of the film, a front-sided wiring pattern embedded in the first insulating resin layer, and a rear-sided wiring pattern embedded in the second insulating resin layer. A surface of the front-sided wiring pattern is flush with a surface of the first insulating resin layer, and a surface of the rear-sided wiring pattern is flush with a surface of the second insulating resin layer. A part of at least one of the front-sided wiring pattern and the rear-sided wiring pattern is dented toward a part of the other of the at least one of the front-sided wiring pattern and the rear-sided wiring pattern such that a portion of the front-sided wiring pattern and a portion of the rear-sided wiring pattern are jointed to each other to form a junction.

公开(公告)号：US08617943B2

公开(公告)日：2013-12-31

申请号：US12746440

申请日：2009-07-22

Applicant: Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano ,  Yoshihisa Yamashita ,  Shingo Komatsu

Inventor： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano ,  Yoshihisa Yamashita ,  Shingo Komatsu

IPC: H01L21/00

CPC classification number: H01L29/78603 ,  H01L24/19 ,  H01L24/82 ,  H01L27/1218 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78681 ,  H01L29/7869 ,  H01L51/0024 ,  H01L51/003 ,  H01L51/0097 ,  H01L51/0541 ,  H01L51/0545 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

Abstract: A method for fabricating a flexible semiconductor device includes: preparing a layered film 80 including a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40 which are sequentially formed; etching the first metal layer 10 to form a gate electrode 12g; compression bonding a resin layer 50 to a surface of the layered film 80 provided with the gate electrode 12g to allow the gate electrode 12g to be embedded in the resin layer 50; and etching the second metal layer 40 to form a source electrode 42s and a drain electrode 42d, wherein the inorganic insulating layer 20 on the gate electrode 12g functions as a gate insulating film 22, and the semiconductor layer 30 between the source electrode 42s and drain electrode 42d on the inorganic insulating layer 20 functions as a channel 32.

Abstract translation: 一种制造柔性半导体器件的方法包括：制备包括依次形成的第一金属层10，无机绝缘层20，半导体层30和第二金属层40的层状膜80; 蚀刻第一金属层10以形成栅电极12g; 将树脂层50压接到设置有栅电极12g的层叠膜80的表面，以使栅电极12g嵌入树脂层50中; 并且蚀刻第二金属层40以形成源电极42s和漏电极42d，其中栅电极12g上的无机绝缘层20用作栅极绝缘膜22，并且源电极42s和漏极之间的半导体层30 无机绝缘层20上的电极42d用作通道32。

公开(公告)号：US08525178B2

公开(公告)日：2013-09-03

申请号：US13498700

申请日：2011-04-14

Applicant: Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano

Inventor： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano

IPC: H01L29/04

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/1292 ,  H01L27/3244 ,  H01L29/78603 ,  H01L2251/5338

Abstract: A flexible semiconductor device includes an insulating film on which a semiconductor element is formed. The top and bottom surfaces of the insulating film have a top wiring pattern layer and a bottom wiring pattern layer, respectively. The semiconductor element includes a semiconductor layer formed on the top surface of the insulating film, a source electrode and a drain electrode formed on the top surface of the insulating film so as to contact the semiconductor layer, and a gate electrode formed on the bottom surface of the insulating film so as to be opposite the semiconductor layer. A first thickness, which is the thickness of the insulating film facing the source electrode, the drain electrode, the top wiring pattern layer, and the bottom wiring pattern layer, is greater than a second thickness, which is the thickness of the insulating film between the gate electrode and the semiconductor layer.

Abstract translation: 柔性半导体器件包括其上形成有半导体元件的绝缘膜。 绝缘膜的顶表面和底表面分别具有顶部布线图案层和底部布线图案层。 半导体元件包括形成在绝缘膜的顶表面上的半导体层，形成在绝缘膜的顶表面上以与半导体层接触的源电极和漏电极，以及形成在底表面上的栅电极 的绝缘膜与半导体层相对。 作为与源极电极，漏极电极，顶部布线图案层和底部布线图案层相对的绝缘膜的厚度的第一厚度大于第二厚度，其是第二厚度，其是绝缘膜的厚度 栅电极和半导体层。

公开(公告)号：US07910403B2

公开(公告)日：2011-03-22

申请号：US11885562

申请日：2006-03-06

Applicant: Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita

Inventor： Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita

IPC: H01L21/00

CPC classification number: H01L24/81 ,  H01L21/6835 ,  H01L23/49883 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/1141 ,  H01L2224/1152 ,  H01L2224/11524 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/293 ,  H01L2224/294 ,  H01L2224/73104 ,  H01L2224/83886 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K3/323 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0425 ,  H05K2203/087 ,  H05K2203/1178 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip chip mounting process wherein a semiconductor chip and a circuit substrate are electrically interconnected. The process includes the steps of preparing a semiconductor chip on which a first plurality of electrodes are formed and a circuit substrate on which a second plurality of electrodes are formed; supplying a composition onto a surface of the circuit substrate, such surface being provided with second plurality of electrodes; bringing the semiconductor chip into contact with a surface of said composition such that the first plurality of electrodes are opposed to the second plurality of electrodes; and heating the circuit substrate, and thereby electrical connections including a metal component constituting the metal particles dispersed in the composition are formed between the first plurality of electrodes and the second plurality of electrodes. Also, a thermoset resin layer is formed between the semiconductor chip and the circuit substrate.

Abstract translation: 一种倒装芯片安装工艺，其中半导体芯片和电路基板电连接。 该方法包括制备其上形成有第一多个电极的半导体芯片和形成有第二多个电极的电路基板的步骤; 在电路基板的表面上提供组合物，该表面设置有第二多个电极; 使所述半导体芯片与所述组合物的表面接触，使得所述第一多个电极与所述第二多个电极相对; 并且加热电路基板，从而在第一多个电极和第二多个电极之间形成包括构成分散在组合物中的金属颗粒的金属组分的电连接。 此外，在半导体芯片和电路基板之间形成热固性树脂层。

公开(公告)号：US07875496B2

公开(公告)日：2011-01-25

申请号：US11914416

申请日：2006-03-30

Applicant: Seiichi Nakatani ,  Seiji Karashima ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu

Inventor： Seiichi Nakatani ,  Seiji Karashima ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC: H01L21/00

CPC classification number: H01L21/563 ,  H01L21/67103 ,  H01L21/67126 ,  H01L23/3135 ,  H01L24/11 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/743 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75743 ,  H01L2224/81121 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8192 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83886 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/381 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0126 ,  H05K2203/082 ,  Y02P70/613 ,  Y10T29/53183 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/00015 ,  H01L2924/0665 ,  H01L2924/0695 ,  H01L2224/05599

Abstract: A flip chip mounting method includes holding a circuit board (213) and a semiconductor chip (206), aligning the circuit board (213) with the semiconductor chip (206) while holding them with a predetermined gap therebetween, heating the circuit board (213) or the semiconductor chip (206) to a temperature at which solder powder in a solder resin composition (216) formed of solder powder (214) and a resin (215) is melted, supplying the solder resin composition (216) by a capillary phenomenon, and curing the resin (215), wherein the melted solder powder (214) in the solder resin composition (216) is moved through the predetermined gap across which the circuit board (213) and the semiconductor chip (206) are held, and self-assembled and grown, whereby the connection terminals (211) and the electrode terminals (207) are connected to each other electrically. According to this configuration, a flip chip mounting method having high productivity and reliability, which enables a next generation semiconductor chip to be mounted on a circuit board, a mounted body thereof, and a mounting apparatus thereof are provided.

Abstract translation: 一种倒装芯片安装方法，包括保持电路板（213）和半导体芯片（206），使电路板（213）与半导体芯片（206）保持一定间隔，同时将电路板（213）加热 ）或半导体芯片（206）的温度升高到由焊料粉末（214）和树脂（215）形成的焊料树脂组合物（216）中的焊料粉末熔化的温度，通过毛细管 现象，固化树脂（215），其中焊料树脂组合物（216）中的熔融焊料粉末（214）移动通过保持电路板（213）和半导体芯片（206）的预定间隙， 并且自组装和生长，由此连接端子（211​​）和电极端子（207）彼此电连接。 根据该结构，提供了一种能够将下一代半导体芯片安装在电路板上的高生产率和可靠性的倒装芯片安装方法及其安装体及其安装装置。

公开(公告)号：US20100203675A1

公开(公告)日：2010-08-12

申请号：US12764455

申请日：2010-04-21

Applicant: Seiichi NAKATANI ,  Takashi KITAE ,  Yoshihisa YAMASHITA ,  Takashi ICHIRYU ,  Seiji KARASHIMA

Inventor： Seiichi NAKATANI ,  Takashi KITAE ,  Yoshihisa YAMASHITA ,  Takashi ICHIRYU ,  Seiji KARASHIMA

IPC: H01L21/60

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/83007 ,  H01L2224/83097 ,  H01L2224/83192 ,  H01L2224/83815 ,  H01L2224/83874 ,  H01L2224/8388 ,  H01L2224/83888 ,  H01L2224/9201 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/0695 ,  H01L2224/05599

Abstract: The flip chip mounted body of the present invention includes: a circuit board (213) having a plurality of connection terminals (211); a semiconductor chip (206) having a plurality of electrode terminals (207) that are disposed opposing the connection terminals (211); and a porous sheet (205) having a box shape that is provided on an opposite side of a formation surface of the electrode terminal (207) of the semiconductor chip (206), is folded on an outer periphery of the semiconductor chip (206) on the formation surface side of the electrode terminal (207) and is in contact with the circuit board (213), wherein the connection terminal (211) of the circuit board (213) and the electrode terminal (207) of the semiconductor chip (206) are connected electrically via a solder layer (215), and the circuit board (213) and the semiconductor chip (206) are fixed by a resin (217). Thereby, the flip chip mounted body with excellent productivity and reliability that can mount the semiconductor chip on the circuit board, and a method and an apparatus for mounting the flip chip mounted body are provided.

Abstract translation: 本发明的倒装芯片安装体包括：具有多个连接端子（211​​）的电路板（213）; 具有与所述连接端子相对设置的多个电极端子（207）的半导体芯片（206）。 在所述半导体芯片（206）的外周折叠具有设置在所述半导体芯片（206）的所述电极端子（207）的形成面的相反侧的盒状的多孔片（205） 在电极端子（207）的形成面侧与电路基板（213）接触，电路基板（213）的连接端子（211​​）和半导体芯片的电极端子（207） 206）通过焊料层（215）电连接，并且电路板（213）和半导体芯片（206）由树脂（217）固定。 因此，提供了将半导体芯片安装在电路板上的优异的生产率和可靠性的倒装芯片安装体以及安装倒装芯片安装体的方法和装置。