公开(公告)号：US09153562B2

公开(公告)日：2015-10-06

申请号：US14574988

申请日：2014-12-18

Applicant: Tessera, Inc.

Inventor： Belgacem Haba ,  Craig S. Mitchell ,  Masud Beroz

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L21/78 ,  H01L23/49575 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In-process units include upper and lower dielectric substrates and a plurality of microelectronic elements disposed between the upper and lower substrates. Each of the upper and lower substrates includes a plurality of regions. Each region of the upper substrate is aligned with a corresponding region of the lower substrate. At least one of the microelectronic elements is disposed between the upper and lower substrates and each of the regions of the upper and lower substrates has interlayer connection terminals at the surface thereof. Vertically elongated electrical conductors are formed from copper and each extend in a vertical direction away from the surface of a dielectric substrate of one of the upper and lower dielectric substrates and have an end joined with an electrically conductive bonding material to the interlayer connection terminal of the region of an other one of the upper and lower dielectric substrates.

Abstract translation: 在处理单元包括上和下介电衬底以及设置在上基板和下基板之间的多个微电子元件。 上基板和下基板中的每一个包括多个区域。 上基板的每个区域与下基板的对应区域对齐。 至少一个微电子元件设置在上基板和下基板之间，并且上基板和下基板的每个区域在其表面具有层间连接端子。 垂直细长的电导体由铜形成，并且各自沿垂直方向延伸远离上述介电基板和上述介电基板之一的电介质基板的表面，并且具有与导电接合材料连接到端子的层间连接端子的端部 上部和下部电介质基板中的另一个的区域。

公开(公告)号：US20150123252A1

公开(公告)日：2015-05-07

申请号：US14248355

申请日：2014-04-09

Applicant: CHIPMOS TECHNOLOGIES INC.

Inventor： TSUNG JEN LIAO

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L23/3107 ,  H01L23/433 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/1191 ,  H01L2224/13147 ,  H01L2224/1626 ,  H01L2224/811 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81897 ,  H01L2224/81904 ,  H01L2224/81951 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The present disclosure relates to a package structure of a lead frame. The package includes a die, a dielectric layer, at least one conducting pillar, at least one lead frame and at least one solder ball. The dielectric layer is disposed on a surface of the die. The at least one conducting pillar penetrates through the dielectric layer and is disposed on the surface. The at least one lead frame is disposed on the dielectric layer and is spaced from the at least one conducting pillar with a gap. The solder ball fills the gap and electrically connects the at least one conducting pillar and the at least one lead frame.

Abstract translation: 本发明涉及引线框的封装结构。 封装包括裸片，电介质层，至少一个导电柱，至少一个引线框和至少一个焊球。 电介质层设置在模具的表面上。 至少一个导柱穿过介电层并设置在表面上。 所述至少一个引线框架设置在所述电介质层上并且与所述至少一个导电柱间隔开间隙。 焊球填充间隙并电连接至少一个导电柱和至少一个引线框架。

公开(公告)号：US20150054173A1

公开(公告)日：2015-02-26

申请号：US14328672

申请日：2014-07-10

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Tae Hyun KIM ,  Do Jae YOO ,  Heung Woo PARK

IPC: H01L23/522 ,  H01L23/31 ,  H01L21/50 ,  H01L21/56

CPC classification number: H01L21/50 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/142 ,  H01L23/145 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L2021/6027 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Disclosed herein are a semiconductor package, a method of manufacturing a semiconductor package, and a stack type semiconductor package. The semiconductor package according to a preferred embodiment of the present invention includes: a base substrate on which a first circuit layer is formed; a semiconductor device formed on the base substrate; a molding part formed on the base substrate and formed to enclose the first circuit layer and the semiconductor device; a first via formed on the first circuit layer and formed to penetrate through the molding part; and a second circuit layer formed on an upper surface of the molding part and integrally formed with the first via.

Abstract translation: 这里公开了半导体封装，半导体封装的制造方法和堆叠型半导体封装。 根据本发明的优选实施例的半导体封装包括：形成有第一电路层的基底基板; 形成在所述基底基板上的半导体器件; 形成在所述基底基板上并形成为封闭所述第一电路层和所述半导体器件的成型部; 第一通孔，其形成在第一电路层上并形成以穿透模制部件; 以及形成在所述模制部件的上表面上并与所述第一通孔一体形成的第二电路层。

公开(公告)号：US08912664B1

公开(公告)日：2014-12-16

申请号：US14195625

申请日：2014-03-03

Applicant: Marvell International Ltd.

Inventor： Shiann-Ming Liou ,  Huahung Kao

IPC: H01L23/48 ,  H01L23/495

CPC classification number: H01L23/4951 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Multi-chip quad flat no-lead (QFN) packages and methods for making the same are disclosed. A multi-chip package may include a first die including a plurality of first bond pads, wherein selected first bond pads are wire-bonded to a first side of a leadframe, and a second die mounted on the first die and including a plurality of second bond pads, wherein selected second bond pads are wire-bonded to a second side, opposite the first side, of the leadframe. Another package may include a first die including a plurality of first bond pads, wherein selected first bond pads are wire-bonded to a first side of a leadframe, and a second die flip-chip mounted on a second side of the leadframe and including a plurality of second bond pads, wherein selected second bond pads are bonded to the second side of the leadframe. Other embodiments are also described.

公开(公告)号：US08872350B2

公开(公告)日：2014-10-28

申请号：US13616549

申请日：2012-09-14

Applicant: Shigenori Sawachi ,  Osamu Yamagata ,  Hiroshi Inoue ,  Satoru Itakura ,  Tomoshige Chikai ,  Masahiko Hori ,  Akio Katsumata

Inventor： Shigenori Sawachi ,  Osamu Yamagata ,  Hiroshi Inoue ,  Satoru Itakura ,  Tomoshige Chikai ,  Masahiko Hori ,  Akio Katsumata

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/02 ,  H01L23/52

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06135 ,  H01L2224/12105 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device containing: a semiconductor element; a support substrate; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part thereof being exposed on an external surface; and metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer. The semiconductor element is provided in a plurality of units and the respective semiconductor elements are stacked via an insulating material such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove.

Abstract translation: 一种半导体器件，包括：半导体元件; 支撑基板; 用于密封半导体元件的绝缘材料层及其周边; 设置在所述绝缘材料层中的金属薄膜布线层，其一部分露出在外表面上; 以及设置在绝缘材料层中并电连接到金属薄膜布线层的金属通孔。 半导体元件设置在多个单元中，并且各个半导体元件经由绝缘材料层叠，使得每个半导体元件的电路表面面对金属薄膜布线层，并且每个半导体元件的电极焊盘暴露而不被隐藏 通过堆叠在其上的半导体元件。

公开(公告)号：US08865525B2

公开(公告)日：2014-10-21

申请号：US13532941

申请日：2012-06-26

Applicant: Charles W. C. Lin ,  Chia Chung Wang

Inventor： Charles W. C. Lin ,  Chia Chung Wang

IPC: H05K1/11 ,  H05K3/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L25/10 ,  H01L21/683 ,  H01L23/367 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/3121 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/24101 ,  H01L2224/24221 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/82106 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/3511 ,  Y10T29/49124 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A method of making a cavity substrate. The method includes: preparing a supporting board including a stiffener, a bump/flange sacrificial carrier, an adhesive and an electrical pad, wherein the adhesive bonds the stiffener to the sacrificial carrier; forming a careless build-up circuitry on the supporting board in contact with the bump and the stiffener; and removing the bump to form a cavity and expose the electrical pad from a closed end of the cavity; wherein the cavity is laterally covered and surrounded by the adhesive. A semiconductor device can be mounted on the cavity substrate and electrically connected to the electrical pad. The careless buildup circuitry provide signal routing for the semiconductor device while the built-in stiffener can provide adequate mechanical support for the careless build-up circuitry and the semiconductor device.

Abstract translation: 一种制造空腔衬底的方法。 该方法包括：制备包括加强件，凸块/凸缘牺牲载体，粘合剂和电垫的支撑板，其中粘合剂将加强件粘合到牺牲载体上; 在与所述凸起和所述加强件接触的所述支撑板上形成粗心的积聚电路; 并且去除所述凸起以形成空腔并使所述电垫从所述空腔的封闭端露出; 其中腔被横向覆盖并被粘合剂包围。 半导体器件可以安装在空腔衬底上并电连接到电焊盘。 不小心积累电路为半导体器件提供信号路由，而内置的加强件可以为不小心的积聚电路和半导体器件提供足够的机械支持。

公开(公告)号：US08841760B2

公开(公告)日：2014-09-23

申请号：US13833766

申请日：2013-03-15

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Kei Murayama

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49503 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49517 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A stacked semiconductor device includes a unit component including a wiring portion formed by electrically connecting a die pad of and a lead of a lead frame, and a semiconductor package whose connection terminal is connected to the lead, wherein the unit component is stacked, and the leads located to upper and lower sides are connected mutually via an electrode.

Abstract translation: 叠层半导体器件包括：单元部件，其包括通过电连接引线框架的管芯焊盘和引线形成的布线部分，以及连接端子连接到引线的半导体封装，其中堆叠单元部件， 位于上侧和下侧的引线经由电极相互连接。

公开(公告)号：US08836136B2

公开(公告)日：2014-09-16

申请号：US13405108

申请日：2012-02-24

Applicant: Ellis Chau ,  Reynaldo Co ,  Roseann Alatorre ,  Philip Damberg ,  Wei-Shun Wang ,  Se Young Yang ,  Zhijun Zhao

Inventor： Ellis Chau ,  Reynaldo Co ,  Roseann Alatorre ,  Philip Damberg ,  Wei-Shun Wang ,  Se Young Yang ,  Zhijun Zhao

IPC: H01L23/48

CPC classification number: H01L24/85 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49517 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/16 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48997 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/851 ,  H01L2224/8518 ,  H01L2224/85399 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1715 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y10T29/49149 ,  Y10T29/49151 ,  H01L2224/45664 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076

Abstract: A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds.

Abstract translation: 微电子封装可以包括引线键合，其具有结合到衬底上的相应导电元件的底部并且与基底相对的端部。 从衬底延伸的电介质封装层覆盖引线接合的部分，使得引线键合的被覆部分通过封装层彼此分离，其中引线键合的未封装部分由未被覆盖的引线键的部分限定 通过封装层。 未封装的部分可以布置在具有最小间距的图案的位置处，该最小间距大于相邻引线键的基部之间的第一最小间距。

公开(公告)号：US20140167262A1

公开(公告)日：2014-06-19

申请号：US13718081

申请日：2012-12-18

Applicant: Weng Foong Yap

Inventor： Weng Foong Yap

IPC: H01L21/56 ,  H01L23/498

CPC classification number: H01L21/56 ,  H01L21/4825 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49517 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85947 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A mechanism is provided by which signal travel distance within and between semiconductor device packages is reduced and substrate size and complexity can be reduced. This capacity is provided by virtue of a conductive via that intersects a wire bond molded within a package substrate. The via provides a direct electrical connection between an external signal transmitter or receiver and the points connected by the wire bond, and thereby avoiding the need for the signal to transit built up interconnects in the semiconductor device package. Conductive vias can provide connectivity through or to a package substrate, and can be through vias or blind vias. The conductive via is formed by either mechanical or laser drilling, and is filled using standard fill techniques, and is therefore readily incorporated into a package production flow.

Abstract translation: 提供了一种减小半导体器件封装内和之间的信号行进距离的机构，并且可以减小衬底大小和复杂性。 该容量由导电通孔提供，导电通孔与模制在封装衬底内的引线接合相交。 通孔提供外部信号发射器或接收器与通过引线接合连接的点之间的直接电连接，从而避免了在半导体器件封装中信号传输建立互连的需要。 导电通孔可以提供通过封装衬底的连接，也可以通过通孔或盲孔。 导电孔通过机械或激光钻孔形成，并且使用标准填充技术填充，因此容易地结合到包装生产流程中。

公开(公告)号：US08729693B2

公开(公告)日：2014-05-20

申请号：US12565144

申请日：2009-09-23

Applicant: Zigmund Ramirez Camacho ,  Arnel Senosa Trasporto ,  Lionel Chien Hui Tay ,  Henry Descalzo Bathan

Inventor： Zigmund Ramirez Camacho ,  Arnel Senosa Trasporto ,  Lionel Chien Hui Tay ,  Henry Descalzo Bathan

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/3107 ,  H01L23/49575 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first device having a first exposed side and a first inward side; connecting a second device having a second exposed side and a second inward side facing the first inward side to the first device, the second device having planar dimensions less than planar dimensions of the first device; connecting a system connector to a perimeter of the first inward side, the system connector having an exposed leg partially vertical and an exposed foot partially horizontal; and applying an encapsulant exposing the first exposed side, the second exposed side, the exposed leg, and the exposed foot, the exposed leg offset from the encapsulant, the exposed foot on an end of the system connector opposite the first device.

Abstract translation: 一种集成电路封装系统的制造方法，包括：提供具有第一暴露侧和第一内侧的第一器件; 将具有第二暴露侧和面向所述第一内侧的第二内侧的第二装置连接到所述第一装置，所述第二装置具有小于所述第一装置的平面尺寸的平面尺寸; 将系统连接器连接到第一内侧的周边，系统连接器具有部分垂直的暴露的腿和暴露的脚部分水平; 以及施加暴露所述第一暴露侧，所述第二暴露侧，所述暴露腿和所述暴露的脚的密封剂，暴露的腿偏离所述密封剂，所述暴露的脚在所述系统连接器的与所述第一装置相对的端部上。