公开(公告)号：US06762119B2

公开(公告)日：2004-07-13

申请号：US09885791

申请日：2001-06-20

Applicant: Sudipta K. Ray ,  Mitchell S. Cohen ,  Lester Wynn Herron ,  Mario J. Interrante ,  Thomas E. Lombardi ,  Subhash L. Shinde

Inventor： Sudipta K. Ray ,  Mitchell S. Cohen ,  Lester Wynn Herron ,  Mario J. Interrante ,  Thomas E. Lombardi ,  Subhash L. Shinde

IPC: H01L2144

CPC classification number: H01S5/02272 ,  G02B6/4238 ,  H01L24/45 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01S5/02236 ,  H01S5/02268 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A process and structure for forming an optical subassembly in an integrated circuit, comprising: defining electrically conducting lines and bonding pads in a metallization layer on a substrate; depositing a passivation layer over the metallization layer; etching the passivation layer to remove the passivation layer from each of the bonding pads and a portion of the metallization layer associated with each of the bonding pads; diffusing Cr from the lines proximate said bonding pads to prevent solder wetting down lines; bonding an optical device to one of the bonding pads; and attaching the substrate to a carrier utilizing solder bond attachment.

Abstract translation: 一种用于在集成电路中形成光学子组件的工艺和结构，包括：在衬底上的金属化层中限定导电线和焊盘; 在所述金属化层上沉积钝化层; 蚀刻钝化层以从每个接合焊盘和与每个焊盘相关联的金属化层的一部分去除钝化层; 从靠近所述接合焊盘的线扩散Cr，以防止焊料向下润湿; 将光学器件接合到所述接合焊盘之一; 以及使用焊料粘合附着将衬底附接到载体上。

公开(公告)号：US06713686B2

公开(公告)日：2004-03-30

申请号：US10053362

申请日：2002-01-18

Applicant: Wiren D. Becker ,  Dinesh Gupta ,  Sudipta K. Ray ,  Robert A. Rita ,  Herbert I. Stoller ,  Kathleen M. Wiley

Inventor： Wiren D. Becker ,  Dinesh Gupta ,  Sudipta K. Ray ,  Robert A. Rita ,  Herbert I. Stoller ,  Kathleen M. Wiley

IPC: H01R1204

CPC classification number: H01L23/5382 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0292 ,  H05K1/113 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A multi chip module substrate arranged with repair vias and repair lines extending between repair vias of the chip sites of the module by which repairs can be effected to overcome defects in the module circuits and a method for effecting the repairs of defects in the circuits of this module. A defect can occur in any one of a first signal via, a second signal via, and a circuit line extending between and intended to electrically connect the first signal via and the second signal via. After a defective circuit is identified, the signal vias of the circuit are isolated. Then, the first signal via of the defective circuit is electrically connected to that repair via of the chip site having the first signal via that is connected to that repair via of the chip site having the second signal via and the second signal via of the defective circuit is electrically connected to that repair via of the chip site having the second signal via that is connected to that repair via of the chip site having the first signal via.

Abstract translation: 多芯片模块基板，其布置有在模块的芯片位置的修复通道之间延伸的修理通孔和修复线，通过该维修线可以进行修理以克服模块电路中的缺陷，以及用于实现该电路中的缺陷的修复的方法 模块。 在第一信号通孔，第二信号通孔以及在第一信号通孔和第二信号通孔之间延伸并且用于电连接第一信号通孔的电路线中的任何一个中可能会发生缺陷。 识别出故障电路后，电路的信号通孔被隔离。 然后，故障电路的第一信号通路经由具有第一信号的芯片位置的修复通孔经由与具有第二信号通路的芯片位置的修复通路连接，并且具有缺陷电路的第二信号通孔 电路经由具有第二信号的芯片位置的修复通路经由与经由具有第一信号通孔的芯片位置的修复通路相连接。

公开(公告)号：US06429388B1

公开(公告)日：2002-08-06

申请号：US09564110

申请日：2000-05-03

Applicant: Mario J. Interrante ,  Brenda Peterson ,  Sudipta K. Ray ,  William E. Sablinski ,  Amit K. Sarkhel

Inventor： Mario J. Interrante ,  Brenda Peterson ,  Sudipta K. Ray ,  William E. Sablinski ,  Amit K. Sarkhel

IPC: H01R909

CPC classification number: B23K35/262 ,  H01L23/488 ,  H01L23/49811 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13109 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01322 ,  H05K3/3426 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/4015 ,  H05K2201/10242 ,  H05K2203/047 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/05599

Abstract: The present invention relates generally to a new semiconductor chip carrier connections, where the chip carrier and the second level assembly are made by a surface mount technology. More particularly, the invention encompasses surface mount technologies, such as, Ball Grid Array (BGA), Column Grid Array (CGA), to name a few, where the surface mount technology comprises essentially of a non-solder metallic connection, such as, a copper connection. The present invention is also related to Column Grid Array structures and process thereof.

Abstract translation: 本发明一般涉及新的半导体芯片载体连接，其中芯片载体和第二级组件是通过表面贴装技术制成的。 更具体地，本发明包括表面贴装技术，例如球栅阵列（BGA），柱栅阵列（CGA），其中表面贴装技术基本上由非焊料金属连接构成，例如， 铜连接。 本发明还涉及列格阵列结构及其工艺。

公开(公告)号：US06235996B1

公开(公告)日：2001-05-22

申请号：US09014804

申请日：1998-01-28

Applicant: Shaji Farooq ,  Mario J. Interrante ,  Sudipta K. Ray ,  William E. Sablinski

Inventor： Shaji Farooq ,  Mario J. Interrante ,  Sudipta K. Ray ,  William E. Sablinski

IPC: H01L2348

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/0215 ,  H05K2201/0272 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613 ,  Y10T29/49126 ,  H01L2924/00

Abstract: An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below +230° C. and detach from the electronic module during subsequent reflows. A Pb—Sn eutectic with a lower melting point is used on the opposite end of the interconnection structure. In the first method a transient melting solder paste is applied to the I/O pad of an electronic module by a screening mask. Interconnect structures are then bonded to the I/O pad. In a second method, solder preforms in a composition of the transient melting solder paste are wetted onto electronic module I/O pads and interconnect columns or balls are then bonded. Detachment of an electronic module from a circuit card can then be performed by heating the circuit card assembly to a temperature above the eutectic solder melting point, but below the transient solder joint melting point.

Abstract translation: 通过使用包括细金属粉末添加剂的电子模块侧的瞬态焊膏来提供柱和球栅阵列（CGA和BGA）结构的互连结构及其分离方法，以增加熔点 的焊点。 金属粉末添加剂改变焊料接合的组成，使得瞬态熔融焊料组合物在低于+ 230℃的温度下不会完全熔化，并且在随后的回流期间与电子模块分离。 在互连结构的另一端使用具有较低熔点的Pb-Sn共晶体。 在第一种方法中，通过屏蔽掩模将瞬态熔融焊膏施加到电子模块的I / O焊盘。 然后将互连结构结合到I / O焊盘。 在第二种方法中，将瞬态熔融焊膏的组合物中的焊料预成型件润湿到电子模块I / O焊盘上，然后将互连柱或球接合。 然后可以通过将电路卡组件加热到高于共熔焊料熔点但低于瞬态焊点熔点的温度来执行从电路卡分离电子模块。

公开(公告)号：US6158644A

公开(公告)日：2000-12-12

申请号：US70163

申请日：1998-04-30

Applicant: Peter J. Brofman ,  Mark G. Courtney ,  Shaji Farooq ,  Mario J. Interrante ,  Raymond A. Jackson ,  Gregory B. Martin ,  Sudipta K. Ray ,  William E. Sablinski ,  Kathleen A. Stalter

Inventor： Peter J. Brofman ,  Mark G. Courtney ,  Shaji Farooq ,  Mario J. Interrante ,  Raymond A. Jackson ,  Gregory B. Martin ,  Sudipta K. Ray ,  William E. Sablinski ,  Kathleen A. Stalter

IPC: H01L23/12 ,  B23K35/02 ,  B23K35/14 ,  H01L21/60 ,  H01L23/498 ,  H05K3/34 ,  B23K35/24 ,  B23K35/26

CPC classification number: H01L24/12 ,  B23K35/0222 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H05K3/3436 ,  B23K35/0244 ,  H01L2224/1184 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K2203/0435 ,  Y02P70/613 ,  Y10T428/12687 ,  Y10T428/2991

Abstract: This invention relates to a solder structure which provides enhanced fatigue life properties when used to bond substrates particularly at the second level such as BGA and CGA interconnections. The solder structure is preferably a sphere or column and has a metal layer wettable by solder and the structure is used to make solder connections in electronic components such as joining an electronic module such as a chip connected to a MLC which module is connected to a circuit board. The solder structure preferably has an overcoat of solder on the metal layer to provide a passivation coating to the metal layer to keep it clean from oxidation and corrosion and also provide a wettable surface for attachment of the solder structure to solder on the pads of the substrate being bonded.

Abstract translation: 本发明涉及一种焊料结构，当用于特别是在第二层（例如BGA和CGA互连）的基材上时，其提供增强的疲劳寿命特性。 焊料结构优选是球形或柱状，并且具有可被焊料润湿的金属层，并且该结构用于在电子部件中形成焊接连接​​，例如连接诸如连接到MLC的芯片的电子模块，该模块连接到电路 板。 焊料结构优选地在金属层上具有焊料的外涂层，以向金属层提供钝化涂层以保持其免于氧化和腐蚀，并且还提供用于将焊料结构附着到衬底的焊盘上的焊料的可润湿表面 被绑定。

公开(公告)号：US5543584A

公开(公告)日：1996-08-06

申请号：US843684

申请日：1992-02-28

Applicant: Edward F. Handford ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  Raymond A. Jackson ,  Raj N. Master ,  Sudipta K. Ray ,  William E. Sablinski ,  Thomas A. Wassick

Inventor： Edward F. Handford ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  Raymond A. Jackson ,  Raj N. Master ,  Sudipta K. Ray ,  William E. Sablinski ,  Thomas A. Wassick

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/498 ,  H01L23/52 ,  H01L23/525 ,  H01L23/538 ,  H05K3/00 ,  H05K3/02 ,  H05K3/22 ,  H05K3/34 ,  H05K1/11

CPC classification number: H01L21/76892 ,  H01L23/49866 ,  H01L23/525 ,  H05K3/225 ,  H01L2924/0002 ,  H05K2201/10181 ,  H05K2201/10234 ,  H05K2201/1028 ,  H05K2201/10287 ,  H05K2203/0769 ,  H05K2203/107 ,  H05K2203/121 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/0017 ,  H05K3/027 ,  H05K3/34 ,  Y10T29/49124

Abstract: The present invention relates generally to a new method of repairing electrical lines, and more particularly to repairing electrical lines having an opening at the module level with devices in place. Various methods and processes are used to repair this open or defective portion in an electrical conductor line. It could be repaired by securing a jumper wire or nugget across the open or the repair could be made by a deposition process, which includes but is not limited to filling the opening with a solder type material or inserting a solder coated electrical wire and heating the solder and allowing the solder to melt and repair the open. One of the attributes of this invention is the ability to repair on a substrate or module on which active components such as chips, and passive components such as pins, capacitors, etc. have been attached. The invention also allows repair of fine line patterns which are normally not repairable by conventional techniques.

Abstract translation: 本发明一般涉及一种修复电线的新方法，更具体地说，涉及在装置的适当位置修复具有模块级开口的电线。 使用各种方法和过程来修复电导体线中的这个开路或有缺陷的部分。 它可以通过将跨接线或熔核固定在整个开口处进行修复，或者可以通过沉积工艺进行修复，该沉积工艺包括但不限于用焊料型材料填充开口或插入焊料涂覆的电线并加热 焊接并允许焊料熔化并修复开路。 本发明的一个特征是在其上附着有诸如引脚，电容器等的诸如芯片和无源部件的有源部件的基板或模块上进行修复的能力。 本发明还允许修复通常不能通过常规技术修复的细线图案。

公开(公告)号：US08450849B2

公开(公告)日：2013-05-28

申请号：US13478076

申请日：2012-05-22

Applicant: Minhua Lu ,  Eric D. Pefecto ,  David L. Questad ,  Sudipta K. Ray

Inventor： Minhua Lu ,  Eric D. Pefecto ,  David L. Questad ,  Sudipta K. Ray

IPC: H01L23/12 ,  H01L21/44

CPC classification number: H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  Y10T29/49117 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: An electrical conductor is connected to a first microcircuit element having a first connector site axis and a second microcircuit having a second connector site axis. The first microcircuit and the second microcircuit are separated by and operatively associated with a first electrical insulator layer. The conductor and the first microcircuit element are separated by and operatively associated with a second electrical insulator layer. At least one of the first electrical insulator layer and the second electrical insulator layer comprise a polymeric material. The microcircuit includes a UBM and solder connection to a FBEOL via opening. Sufficiently separating the first connector site axis and the second connector site axis so they are not concentric, decouples the UBM and solder connection to the FBEOL via opening. This eliminates or minimizes electromigration and the white bump problems. A process comprises manufacturing the microcircuit.

Abstract translation: 电导体连接到具有第一连接器位置轴的第一微电路元件和具有第二连接器位置轴的第二微电路。 第一微电路和第二微电路由第一电绝缘体层分离并且与第一电绝缘体层可操作地相关联。 导体和第一微电路元件由第二电绝缘体层分离并且可操作地与第二电绝缘体层相连。 第一电绝缘体层和第二电绝缘体层中的至少一个包含聚合材料。 微电路包括UBM和通过开口焊接到FBEOL的焊接。 将第一连接器位置轴和第二连接器位置轴线充分分离，使其不同心，通过打开将UBM和焊接连接断开到FBEOL。 这消除或最小化电迁移和白色凸起问题。 一种方法包括制造微电路。

公开(公告)号：US20110291261A1

公开(公告)日：2011-12-01

申请号：US12789316

申请日：2010-05-27

Applicant: Thomas J. Fleischman ,  Eric D. Perfecto ,  Sudipta K. Ray

Inventor： Thomas J. Fleischman ,  Eric D. Perfecto ,  Sudipta K. Ray

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L25/0657 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06051 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06177 ,  H01L2224/06181 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01028 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An apparatus, system, and method are disclosed for connecting integrated circuit devices. A plurality of primary electrically conductive contacts and a plurality of primary electrically conductive pillars are electrically coupled to a primary integrated circuit device. The plurality of primary electrically conductive contacts form a pattern corresponding to secondary electrically conductive contacts disposed on one or more secondary integrated circuit devices. The plurality of primary electrically conductive pillars extends away from the primary integrated circuit device. The plurality of primary electrically conductive pillars forms a pattern that corresponds to substrate electrically conductive contacts that are disposed on a substrate. The plurality of primary electrically conductive pillars and associated connecting material provide a standoff height between the primary integrated circuit device and the substrate that is greater than or equal to a height of the one or more secondary integrated circuit devices.

Abstract translation: 公开了用于连接集成电路器件的装置，系统和方法。 多个初级导电触点和多个初级导电柱电耦合到初级集成电路器件。 多个初级导电触点形成对应于设置在一个或多个次级集成电路器件上的次级导电触点的图案。 多个主导电支柱远离主集成电路装置延伸。 多个主导电柱形成对应于设置在基板上的基板导电触点的图案。 多个初级导电柱和相关联的连接材料提供主集成电路器件和衬底之间的间隔高度，其大于或等于一个或多个次级集成电路器件的高度。

公开(公告)号：US06984792B2

公开(公告)日：2006-01-10

申请号：US10427459

申请日：2003-05-01

Applicant: Peter J. Brofman ,  Shaji Farooq ,  John U. Knickerbocker ,  Scott I. Langenthal ,  Sudipta K. Ray ,  Kathleen A. Stalter

Inventor： Peter J. Brofman ,  Shaji Farooq ,  John U. Knickerbocker ,  Scott I. Langenthal ,  Sudipta K. Ray ,  Kathleen A. Stalter

IPC: H01R12/06

CPC classification number: H05K3/3436 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/09701 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10674 ,  H05K2203/0415 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49149 ,  H01L2224/05599

Abstract: A pre-thermal reflown dielectric interposer having a plurality of vias traversing through the interposer which correspond to the I/O pads on a chip and substrate. Cone shaped solder elements reside within the vias, whereby these solder elements are cone shaped prior to thermal reflow to permit a reduced force for allowing some non-planarity for joining the chip to the substrate. The interposer may comprise a polyester film, glass, alumina, polyimide, a heat curable polymer or an inorganic powder filler in an organic material. The interposer may also have an adhesive or adhesive layers disposed on the linear surfaces thereof. The present pre-thermal reflown interposer prohibits contact between the solder joints by isolating each of the joints and corresponding bonding pads, as well as preventing over compression of the solder joints by acting as a stand off.

Abstract translation: 具有穿过插入件的多个通孔对应于芯片和基板上的I / O焊盘的预热退火介电插入器。 锥形焊料元件驻留在通孔内，由此这些焊料元件在热回流之前是锥形的，以允许减小的力以允许用于将芯片连接到衬底的一些非平面性。 中间层可以在有机材料中包含聚酯膜，玻璃，氧化铝，聚酰亚胺，热固化聚合物或无机粉末填料。 插入器也可以具有设置在其线性表面上的粘合剂或粘合剂层。 本发明的预热反射中介层通过隔离每个接头和相应的接合焊盘来防止焊点之间的接触，并且通过作为脱开来防止焊点过度压缩。

公开(公告)号：US06908025B2

公开(公告)日：2005-06-21

申请号：US10604111

申请日：2003-06-26

Applicant: Patrick A. Coico ,  Steven P. Ostrander ,  Sudipta K. Ray

Inventor： Patrick A. Coico ,  Steven P. Ostrander ,  Sudipta K. Ray

IPC: B23K1/018 ,  B23K31/02 ,  B23K31/00

CPC classification number: B23K1/018 ,  Y10T29/4973 ,  Y10T29/4975 ,  Y10T29/49824

Abstract: A process and apparatus for preparing an MCM for hat removal where the hat includes a piston thermally coupled to a corresponding chip. The apparatus includes a heater positioned to reflow a joint between the piston and a base of the hat; and a retractor for biasing the piston away from the corresponding chip. Implementation of the apparatus and process prevent a piston, as it moves across the top of a corresponding chip during mechanical shear to remove the hat, to impact chip(s) and surrounding components. In addition, since piston(s) are retracted, the likelihood of piston impact with or cracking of a chip is reduced. In addition, cutting into a corresponding chip having a tilted back surface is prevented. The need to replace chips and other electronic components when making other repairs may, therefore, be greatly reduced.

Abstract translation: 一种制备用于帽子去除的MCM的方法和装置，其中帽子包括热耦合到相应芯片的活塞。 该装置包括加热器，该加热器定位成回流活塞和帽子的基座之间的接头; 以及用于将活塞偏压离开相应芯片的牵开器。 该设备和过程的实施防止活塞在机械剪切过程中跨过相应芯片的顶部移动以去除帽子，以冲击芯片和周围部件。 此外，由于活塞缩回，因此减少了活塞撞击或碎裂的可能性。 此外，防止切入具有倾斜背面的相应芯片。 因此，在进行其他维修时需要更换芯片和其他电子部件可能会大大降低。