-
公开(公告)号：US20070289773A1
公开(公告)日：2007-12-20
申请号：US11454896
申请日：2006-06-19
申请人： David V. Caletka , Frank D. Egitto
发明人： David V. Caletka , Frank D. Egitto
CPC分类号： H05K1/0219 , H01R12/523 , H01R13/2414 , H05K1/113 , H05K3/4046 , H05K3/429 , H05K3/4614 , H05K2201/0959 , H05K2201/09809 , H05K2201/10303 , H05K2201/10378 , Y10T29/49155 , Y10T29/49165
摘要： A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.
摘要翻译： 高速插入器，其包括具有交替取向的介电层和导电层的基板，其形成基板，从基板的一个相对表面延伸到第二相对表面的开口，定位在开口内并且还从表面延伸到表面的导电构件 并且在一些实施例中超越）以及基本上围绕导电构件定位的多个屏蔽构件，从而在高频信号通过导电构件期间提供屏蔽。
-
32.发明授权Method of treating conductive layer for use in a circuitized substrate and method of making said substrate having said conductive layer as part thereof 有权用于电路化基板的导电层的处理方法以及制造具有所述导电层作为其一部分的所述基板的方法公开(公告)号：US07307022B2
公开(公告)日：2007-12-11
申请号：US11327493
申请日：2006-01-09
CPC分类号： H05K3/384 , H05K1/056 , H05K3/386 , H05K2201/0355 , H05K2201/0358 , H05K2203/0353 , H05K2203/0723
摘要： A method of treating a conductive layer to assure enhanced adhesion of the layer to selected dielectric layers used to form a circuitized substrate. The conductive layer includes at least one surface with the appropriate roughness to enable such adhesion and also good signal passage if the layer is used as a signal layer. The method is extendible to the formation of such substrates, including to the formation of multilayered substrates having many conductive and dielectric layers. Such substrates may include one or more electrical components (e.g., semiconductor chips) mounted thereon and may also be mounted themselves onto other substrates.
摘要翻译： 一种处理导电层以确保该层对用于形成电路化基底的所选电介质层的附着力的方法。 导电层包括具有适当粗糙度的至少一个表面以实现这种粘附，并且如果该层用作信号层，则还具有良好的信号通过。 该方法可扩展到形成这种衬底，包括形成具有许多导电和电介质层的多层衬底。 这样的基板可以包括安装在其上的一个或多个电气部件（例如，半导体芯片），并且也可以将它们本身安装到其它基板上。
-
公开(公告)号：US07185428B2
公开(公告)日：2007-03-06
申请号：US10738705
申请日：2003-12-16
IPC分类号： H05K3/02
CPC分类号： H05K3/06 , B32B15/08 , B32B15/20 , B32B27/04 , B32B27/06 , B32B27/30 , B32B27/38 , H01L21/32134 , H01L21/4846 , H01L21/76838 , H01L2924/0002 , H05K3/027 , H05K3/061 , H05K3/064 , H05K2203/0369 , H05K2203/1476 , Y10T29/49117 , Y10T29/49124 , Y10T29/49139 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T428/24322 , Y10T428/24802 , H01L2924/00
摘要： A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.
摘要翻译： 提供电路化基板和制造电路化基板的方法。 电路化基板包括具有基本平坦的上表面的基板和位于基本平坦的上表面上的导电层。 导电层包括其中的至少一个侧壁，在导电层中限定开口。 所述导电层包括与所述开口间隔开的端部，所述端部与所述基板的大致平坦的上表面形成锐角。 所述至少一个侧壁基本上垂直于所述基底的基本平坦的上表面。
-
公开(公告)号：US06822332B2
公开(公告)日：2004-11-23
申请号：US10253439
申请日：2002-09-23
IPC分类号： H01L2348
CPC分类号： H05K3/06 , B32B15/08 , B32B15/20 , B32B27/04 , B32B27/06 , B32B27/30 , B32B27/38 , H01L21/32134 , H01L21/4846 , H01L21/76838 , H01L2924/0002 , H05K3/027 , H05K3/061 , H05K3/064 , H05K2203/0369 , H05K2203/1476 , Y10T29/49117 , Y10T29/49124 , Y10T29/49139 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T428/24322 , Y10T428/24802 , H01L2924/00
摘要： A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.
摘要翻译： 提供电路化基板和制造电路化基板的方法。 电路化基板包括具有基本平坦的上表面的基板和位于基本平坦的上表面上的导电层。 导电层包括其中的至少一个侧壁，在导电层中限定开口。 所述导电层包括与所述开口间隔开的端部，所述端部与所述基板的大致平坦的上表面形成锐角。 所述至少一个侧壁基本上垂直于所述基底的基本平坦的上表面。
-
35.发明授权公开(公告)号：US06770968B2
公开(公告)日：2004-08-03
申请号：US10369778
申请日：2003-02-19
IPC分类号： H01L2334
CPC分类号： B29C59/14 , H01L21/56 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2924/15311 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： A method for bonding heat sinks to packaged electronic components comprises the steps of: (a) exposing to a plasma a surface of a molded polymer formed on a substrate; (b) allowing the plasma to at least partially convert silicon-containing residue on the surface to silica; and (c) bonding an article to the surface by applying an adherent between the article and the surface. Often, the silicon-containing residue is silicone oil, a mold release compound, which may prevent the formation of a bond when using conventional bonding methods and materials. The silica layer formed on the surface of the molded polymer assists in formation of a proper bond. The plasma may be an oxygen plasma and the adherent may be selected from either a heat cured silicone-based paste adhesive with a metal oxide filler or a heat cured porous polymer film impregnated with adhesive. In particular, the film may be polytetrafluoroethylene, the adhesive may be polybutadine, and the film may be further impregnated with a metal oxide heat transfer medium, such as zinc oxide. An alternate method comprises applying the porous polymer film without plasma treatment and heat curing the film to form a proper bond.
摘要翻译： 一种用于将散热器粘合到封装的电子部件的方法包括以下步骤：（a）将形成在基底上的模制聚合物的表面暴露于等离子体; （b）允许等离子体至少部分地将表面上的含硅残余物转化为二氧化硅; 和（c）通过在制品和表面之间施加贴附物将物品粘合到表面上。 通常，含硅残渣是使用常规粘合方法和材料的硅油，脱模剂，可以防止形成粘结。 形成在模塑聚合物表面上的二氧化硅层有助于形成适当的键。 等离子体可以是氧等离子体，并且粘合剂可以选自具有金属氧化物填料的热固化的硅氧烷基糊状粘合剂或浸渍有粘合剂的热固化多孔聚合物膜。 特别地，膜可以是聚四氟乙烯，粘合剂可以是聚丁二烯，并且该膜可以进一步用金属氧化物传热介质如氧化锌浸渍。 替代方法包括在不进行等离子体处理的情况下应用多孔聚合物膜并热固化膜以形成适当的键。
-
公开(公告)号：US06576996B2
公开(公告)日：2003-06-10
申请号：US09757159
申请日：2001-01-09
IPC分类号： H01L2334
CPC分类号： B29C59/14 , H01L21/56 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2924/15311 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： A method for bonding heat sinks to packaged electronic components comprises the steps of: (a) exposing to a plasma a surface of a molded polymer formed on a substrate; (b) allowing the plasma to at least partially convert silicon-containing residue on the surface to silica; and (c) bonding an article to the surface by applying an adherent between the article and the surface. Often, the silicon-containing residue is silicone oil, a mold release compound, which may prevent the formation of a bond when using conventional bonding methods and materials. The silica layer formed on the surface of the molded polymer assists in formation of a proper bond. The plasma may be an oxygen plasma and the adherent may be selected from either a heat cured silicone-based paste adhesive with a metal oxide filler or a heat cured porous polymer film impregnated with adhesive. In particular, the film may be polytetrafluoroethylene, the adhesive may be polybutadine, and the film may be further impregnated with a metal oxide heat transfer medium, such as zinc oxide. An alternate method comprises applying the porous polymer film without plasma treatment and heat curing the film to form a proper bond.
-
公开(公告)号：US06348738B1
公开(公告)日：2002-02-19
申请号：US09371975
申请日：1999-08-11
申请人： Jean Dery , Frank D. Egitto , Luis J. Matienzo , Charles Ouellet , Luc Ouellet , David L. Questad , William J. Rudik , Son K. Tran
发明人： Jean Dery , Frank D. Egitto , Luis J. Matienzo , Charles Ouellet , Luc Ouellet , David L. Questad , William J. Rudik , Son K. Tran
IPC分类号： H01L2348
CPC分类号： H01L24/28 , H01L21/563 , H01L24/45 , H01L2224/16 , H01L2224/45124 , H01L2224/45144 , H01L2224/73203 , H01L2224/73204 , H01L2224/81191 , H01L2224/83102 , H01L2224/92125 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01033 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , Y10S438/959 , H01L2924/3512 , H01L2924/00 , H01L2224/29099 , H01L2224/48
摘要： A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O2 plasma or a microwave-generated Ar and N2O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treated with the plasma before they are joined to one another. The plasma treatment improves adhesion between the encapsulant and the IC chip, and between the encapsulant and the chip carrier.
摘要翻译： 一种用于形成板上倒装芯片组件的方法。 具有聚酰亚胺钝化层的集成电路（IC）芯片通过将IC芯片上的多个接触焊盘电连接到芯片载体上的相应触点的多个焊料凸块而接合到芯片载体。 在钝化层的表面和芯片载体的表面之间形成空间。 施加等离子体以化学改性芯片载体的表面和IC芯片的钝化层，基本上不使钝化层的表面变粗糙。 等离子体是O2等离子体或微波产生的Ar和N2O等离子体。 应用底部填充密封材料填充空间。 等离子体处理可以在接合步骤之后进行。 然后，同时用等离子体处理芯片和芯片载体。 或者，IC芯片和芯片载体可以在彼此接合之前用等离子体处理。 等离子体处理改善了密封剂和IC芯片之间以及密封剂和芯片载体之间的粘合性。
-
公开(公告)号：US06203652B1
公开(公告)日：2001-03-20
申请号：US09345326
申请日：1999-06-30
申请人： Frank D. Egitto , John S. Kresge
发明人： Frank D. Egitto , John S. Kresge
IPC分类号： B32B3118
CPC分类号： H05K3/0032 , H05K3/0035 , H05K2203/1383 , Y10T29/49165 , Y10T156/1057
摘要： A method of forming a via in a substrate is provided. The method generally includes laminating a support to the substrate, forming the via in the substrate, and then stripping the support from the substrate. The support is preferably a photoresist that collects any debris generated by the via formation so that the debris is removed from the via and substrate surface as the photoresist support is stripped.
摘要翻译： 提供了在基板中形成通孔的方法。 该方法通常包括将支撑物层压到基底上，在基底中形成通孔，然后从基底剥离载体。 载体优选是光致抗蚀剂，其收集由通孔形成物产生的任何碎屑，使得当光致抗蚀剂载体被剥离时，碎屑从通孔和基底表面除去。
-
公开(公告)号：US5626771A
公开(公告)日：1997-05-06
申请号：US470270
申请日：1995-06-06
IPC分类号： H05K1/03 , H01L21/48 , H01L23/14 , H01L23/498 , H01L23/538 , H05K1/00 , H05K3/00 , H05K3/46 , H01L21/268
CPC分类号： H05K3/0035 , H01L21/4857 , H01L21/486 , H01L23/142 , H01L23/145 , H01L23/49894 , H01L23/5384 , H01L2924/0002 , H05K1/034 , H05K1/0373 , H05K2201/0195 , H05K2203/0207 , H05K3/4602 , H05K3/4641 , H05K3/4644 , H05K3/4676 , Y10T428/24917 , Y10T428/25 , Y10T428/252 , Y10T428/3154 , Y10T428/31721
摘要： A multi-layer electronic circuit package including at least one electrically conductive plane, a first organic polymeric dielectric material having a first optical absorbency to an ablating wavelength of laser light, and a second organic polymeric dielectric material having a second optical absorbency to the ablating wavelength of laser light. The first and second optical absorbencies being different from each other. A first layer of one of the organic polymeric materials overlays at least one surface of the at least one electrically conductive plane and a second layer of a different organic polymeric material with a different optical absorbency to the material in the first layer overlays the first layer.
摘要翻译： 一种多层电子电路封装，包括至少一个导电平面，对激光的消融波长具有第一光学吸收性的第一有机聚合物电介质材料和具有对消融波长的第二光学吸收性的第二有机聚合物电介质材料 的激光。 第一和第二光吸收率彼此不同。 有机聚合材料之一的第一层覆盖至少一个导电平面的至少一个表面，并且具有与第一层中的材料不同的光学吸收性的不同有机聚合物材料的第二层覆盖在第一层上。
-
40.发明授权Materials and methods for plasma etching of oxides and nitrides of silicon 失效用于等离子体蚀刻硅的氧化物和氮化物的材料和方法
公开(公告)号：US4376672A
公开(公告)日：1983-03-15
申请号：US315133
申请日：1981-10-26
申请人： David N. Wang , Frank D. Egitto , Dan Maydan
发明人： David N. Wang , Frank D. Egitto , Dan Maydan
IPC分类号： C01B33/113 , B01J19/08 , C01B21/068 , C03C15/00 , C09K13/08 , C23F1/00 , C23F4/00 , H01L21/302 , H01L21/3065 , H01L21/311 , B44C1/22 , C03C25/06 , H01L21/306
CPC分类号： H01L21/31116 , C23F4/00 , Y10S148/131
摘要： A method for etching a layer of inorganic insulating material formed on a semiconductor wafer and containing silicon as the principal metallic element. The method involves disposing a wafer on one of a pair of electrode structures in a closed chamber. A reactive gas mixture comprising principally a fluorocarbon gas doped with a preselected quantity of carbon dioxide is supplied to the chamber.Radio frequency electrical energy is supplied to one of the electrode structures to create a plasma of the reactive gas mixture for chemically attacking the insulating material.
摘要翻译： 一种用于蚀刻形成在半导体晶片上并含有硅作为主要金属元素的无机绝缘材料层的方法。 该方法包括将晶片放置在封闭室中的一对电极结构中的一个上。 将主要包含掺杂有预选量的二氧化碳的碳氟化合物气体的反应性气体混合物供应到室。 将射频电能提供给电极结构之一以产生用于化学侵蚀绝缘材料的反应气体混合物的等离子体。
-
-
-
-
-
-
-
-
-
搜索结果
101 条记录 (耗时 0.03 秒)
