公开(公告)号：US11682677B2

公开(公告)日：2023-06-20

申请号：US17371450

申请日：2021-07-09

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki

IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L27/146 ,  H01L29/417 ,  H01L21/02 ,  H01L29/04 ,  H01L29/08 ,  H01L29/24 ,  H10B41/70 ,  H01L27/1156

CPC分类号： H01L27/1229 ,  H01L21/02565 ,  H01L21/02672 ,  H01L27/1225 ,  H01L27/14632 ,  H01L27/14687 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L27/1156

摘要： A region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are formed separately in one oxide semiconductor film. The region containing a high proportion of crystal components is formed so as to serve as a channel formation region and the other region is formed so as to contain a high proportion of amorphous components. It is preferable that an oxide semiconductor film in which a region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are mixed in a self-aligned manner be formed. To separately form the regions which differ in crystallinity in the oxide semiconductor film, first, an oxide semiconductor film containing a high proportion of crystal components is formed and then process for performing amorphization on part of the oxide semiconductor film is conducted.

公开(公告)号：US20230154975A1

公开(公告)日：2023-05-18

申请号：US18096791

申请日：2023-01-13

申请人： STMicroelectronics (Rousset) SAS

发明人： Pascal FORNARA

IPC分类号： H01L29/04 ,  H01L29/66 ,  H01L29/861 ,  H01L29/868

CPC分类号： H01L29/04 ,  H01L29/6609 ,  H01L29/8615 ,  H01L29/868

摘要： A PIN diode includes a first polycrystalline silicon region doped with a P-type of conductivity, a second polycrystalline silicon region doped with an N-type of conductivity and an intrinsic polycrystalline silicon region. At least the intrinsic polycrystalline silicon region is configured to include fluorine atoms. A polycrystalline silicon bar may include the first polycrystalline silicon region, the second polycrystalline silicon region and the intrinsic polycrystalline silicon region. The polycrystalline silicon bar may be supported by an insulating region within a semiconductor substrate.

公开(公告)号：US11646380B2

公开(公告)日：2023-05-09

申请号：US17564518

申请日：2021-12-29

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Masayuki Sakakura ,  Hideomi Suzawa

IPC分类号： H01L29/786 ,  H01L29/04 ,  H01L27/105 ,  H01L27/12 ,  H01L27/146 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/78696 ,  H01L27/1225 ,  H01L27/14616 ,  H01L29/04 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H10B99/00 ,  H01L29/7854

摘要： A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.

公开(公告)号：US20190245075A1

公开(公告)日：2019-08-08

申请号：US16385817

申请日：2019-04-16

申请人： Infineon Technologies AG

发明人： Thomas Aichinger ,  Dethard Peters ,  Ralf Siemieniec

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16 ,  H01L29/04 ,  H01L29/739 ,  H01L29/423 ,  H01L27/02 ,  H01L27/06

CPC分类号： H01L29/7804 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0727 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/861

摘要： A semiconductor device includes a plurality of gate trenches formed in a first surface of a semiconductor body and extending lengthwise parallel to one another, transistor cells and diode regions formed in a mesa of the semiconductor body between neighboring ones of the gate trenches, and a drift region in the semiconductor body beneath the gate trenches. Each transistor cell includes a source zone and a body region. Each diode region includes a contact portion and a lower doped shielding portion. The source zone forms a first p-n junction with the body region, and the body region forms a second p-n junction with the drift region. The contact region extends to the first surface, and the shielding portion forms a third p-n junction with the drift region. The shielding portion extends under bottoms of the neighboring ones of the gate trenches.

公开(公告)号：US20190237367A1

公开(公告)日：2019-08-01

申请号：US16372717

申请日：2019-04-02

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio MASUOKA ,  Nozomu HARADA ,  Hiroki NAKAMURA ,  Phillipe MATAGNE ,  Yoshiaki KIKUCHI

IPC分类号： H01L21/8238 ,  H01L21/225 ,  H01L21/28 ,  H01L21/308 ,  H01L21/768 ,  H01L27/11 ,  H01L29/16 ,  H01L29/51 ,  H01L29/49

CPC分类号： H01L21/823828 ,  H01L21/2018 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/28132 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/04 ,  H01L29/0657 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/7827

摘要： The method for producing a pillar-shaped semiconductor device includes a step of forming a tubular SiO2 layer that surrounds side surfaces of a P+ layer 38a and N+ layers 38b and 8c formed on a Si pillar 6b by epitaxial crystal growth, forming an AlO layer 51 on a periphery of the SiO2 layer, forming a tubular contact hole by etching the tubular SiO2 layer using the AlO layer 51 as a mask, and filling the contact hole with W layers 52c, 52d, and 52e to form tubular W layers 52c, 52d, and 52e (including a buffer conductor layer) that have an equal width when viewed in plan and are in contact with side surfaces of the tops of the P+ layer 38a and the N+ layers 38b and 8c.

公开(公告)号：US20190186041A1

公开(公告)日：2019-06-20

申请号：US15849088

申请日：2017-12-20

申请人： International Business Machines Corporation

发明人： Alexander Reznicek ,  Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Keith E. Fogel

IPC分类号： C30B29/06 ,  H01L29/16 ,  H01L29/04 ,  H01L29/06 ,  H01L21/683 ,  H01L21/02 ,  H01L23/498 ,  C30B25/18

CPC分类号： C30B29/06 ,  C30B25/18 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/6835 ,  H01L23/4985 ,  H01L29/04 ,  H01L29/0657 ,  H01L29/16 ,  H01L2221/68345 ,  H01L2221/68381

摘要： A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.

公开(公告)号：US20190157417A1

公开(公告)日：2019-05-23

申请号：US16010454

申请日：2018-06-16

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Pouya Hashemi ,  Tak H. Ning ,  Alexander Reznicek

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/04 ,  H01L29/20 ,  H01L29/732 ,  H01L29/10

CPC分类号： H01L29/6631 ,  H01L29/04 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/20 ,  H01L29/7325

摘要： A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Homojunction and heterojunction devices are formed using III-V compound semiconductor materials with appropriate bandgaps. Fabrication of the transistor device includes epitaxially growing a III-V compound semiconductor base region on a heavily doped III-V compound semiconductor bottom layer. A polycrystalline emitter/collector layer and the all-around extrinsic base are grown on the base region.

公开(公告)号：US20190157416A1

公开(公告)日：2019-05-23

申请号：US15818377

申请日：2017-11-20

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Pouya Hashemi ,  Tak H. Ning ,  Alexander Reznicek

IPC分类号： H01L29/66 ,  H01L29/04 ,  H01L29/20 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

CPC分类号： H01L29/6631 ,  H01L29/04 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/20 ,  H01L29/7325

摘要： A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Homojunction and heterojunction devices are formed using III-V compound semiconductor materials with appropriate bandgaps. Fabrication of the transistor device includes epitaxially growing a III-V compound semiconductor base region on a heavily doped III-V compound semiconductor bottom layer. A polycrystalline emitter/collector layer and the all-around extrinsic base are grown on the base region.

公开(公告)号：US20180366473A1

公开(公告)日：2018-12-20

申请号：US16029440

申请日：2018-07-06

申请人： Cypress Semiconductor Corporation

发明人： Ming Sang Kwan ,  Shenqing Fang ,  Youseok Suh ,  Michael A. VAN BUSKIRK

IPC分类号： H01L27/1157 ,  G11C16/16 ,  H01L27/11582 ,  G11C16/14 ,  G11C16/04 ,  H01L29/16 ,  H01L29/04 ,  H01L29/51 ,  H01L23/528

CPC分类号： H01L27/1157 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/16 ,  H01L23/528 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L29/513 ,  H01L29/518 ,  Y10T29/49002

摘要： A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.

公开(公告)号：US20180350908A1

公开(公告)日：2018-12-06

申请号：US16054457

申请日：2018-08-03

申请人： Advanced Silicon Group, Inc.

发明人： Brent A. Buchine ,  Marcie R. Black ,  Faris Modawar

IPC分类号： H01L29/06 ,  H01L21/308 ,  B01J20/28 ,  B82Y20/00 ,  B82Y30/00 ,  C23C14/34 ,  H01L21/02 ,  H01M4/38 ,  H01M4/36 ,  H01M4/134 ,  H01M4/04 ,  H01L31/0352 ,  H01L31/028 ,  H01L31/0236 ,  H01L29/16 ,  H01L29/04 ,  H01L21/3213 ,  B01J20/10 ,  H01L21/306 ,  H01L21/285 ,  H01M4/1395 ,  H01M4/66 ,  H01M10/0525 ,  H01M4/02

CPC分类号： H01L29/0669 ,  B01J20/10 ,  B01J20/28007 ,  B82Y20/00 ,  B82Y30/00 ,  C23C14/34 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02282 ,  H01L21/02307 ,  H01L21/0234 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/32134 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/16 ,  H01L31/0236 ,  H01L31/02363 ,  H01L31/028 ,  H01L31/0352 ,  H01M4/0492 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/366 ,  H01M4/386 ,  H01M4/661 ,  H01M10/0525 ,  H01M2004/027 ,  Y02E10/50 ,  Y10S977/762

摘要： A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures includes depositing metal on top of the substrate and contacting the metallized substrate with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent.