公开(公告)号：US20100230144A1

公开(公告)日：2010-09-16

申请号：US11340298

申请日：2006-01-26

Applicant: Christopher Schreiber ,  Christopher Dunn

Inventor： Christopher Schreiber ,  Christopher Dunn

IPC: H05K1/09

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/16 ,  H05K3/4076 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09827 ,  Y10T428/30 ,  Y10T428/31678

Abstract: A disk drive suspension interconnect, and method therefor. The interconnect has a metal grounding layer, a metal conductive layer and an insulative layer between the metal grounding layer and the conductive metal layer. A circuit component such as a slider is electrically connected to the conductive layer along a grounding path from the circuit component and the conductive layer to the metal grounding layer through an aperture in the insulative layer. For improved electrical connection a tie layer is provided through the insulative layer onto the grounding layer in bonding relation with the ground layer. A conductor is deposited onto both the conductive metal layer and the tie layer in conductive metal layer and tie layer bonding relation, and the circuit component is thus bonded to the grounding layer by the conductor.

Abstract translation: 磁盘驱动器悬挂互连及其方法。 互连在金属接地层和导电金属层之间具有金属接地层，金属导电层和绝缘层。 诸如滑块的电路部件沿着从电路部件和导电层到金属接地层的通过绝缘层的孔的接地路径电连接到导电层。 为了改善电连接，通过绝缘层将接合层提供到与接地层结合的接地层上。 导电体以导电金属层和连接层结合关系沉积在导电金属层和连接层两者上，并且电路部件因此被导体结合到接地层。

公开(公告)号：US07790503B2

公开(公告)日：2010-09-07

申请号：US11958603

申请日：2007-12-18

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

IPC: H01L21/00

CPC classification number: H01L23/50 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/20 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09736 ,  H05K2203/016 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing a semiconductor device includes providing a substrate with an insulation layer disposed on a top surface of the substrate, forming a passive device over the top surface of the substrate, removing the substrate, depositing an insulating polymer film layer over the insulation layer, and depositing a metal layer over the insulating polymer film layer. A solder mask can be formed over the metal layer. A conformal metal layer can then be formed over the solder mask. A notch can be formed in the insulation layer to enhance the connection between the insulating polymer film layer and the insulation layer. Additional semiconductor die can be electrically connected to the passive device. The substrate is removed by removing a first amount of the substrate using a back grind process, and then removing a second amount of the substrate using a wet dry, dry etch, or chemical-mechanical planarization process.

Abstract translation: 一种制造半导体器件的方法包括：在衬底的顶表面上设置绝缘层，在衬底的顶表面上形成无源器件，去除衬底，在绝缘层上沉积绝缘聚合物膜层 并且在绝缘聚合物膜层上沉积金属层。 可以在金属层上形成焊接掩模。 然后可以在焊接掩模上形成保形金属层。 可以在绝缘层中形成切口以增强绝缘聚合物膜层和绝缘层之间的连接。 另外的半导体管芯可以电连接到无源器件。 通过使用后研磨工艺去除第一量的基材，然后使用湿干，干蚀刻或化学机械平面化工艺除去第二量的基材来除去基材。

公开(公告)号：US07777136B2

公开(公告)日：2010-08-17

申请号：US11873435

申请日：2007-10-17

Applicant: Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

Inventor： Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4641 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1092

Abstract: A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

Abstract translation: 多层互连结构和形成方法。 在第一实施例中，第一和第二液晶聚合物（LCP）电介质层分别直接接合到导热层的第一和第二相对表面，没有外在粘合材料将导热层与第一或第二液晶聚合物 LCP电介质层。 在第二实施例中，第一和第二2S1P子结构分别直接接合到LCP电介质接合层的第一和第二相对表面，没有外部粘合材料将LCP电介质接合层与第一或第二2S1P子结构结合。

公开(公告)号：US20100193231A1

公开(公告)日：2010-08-05

申请号：US12696962

申请日：2010-01-29

Applicant: Kimihiro YAMANAKA ,  Manabu ICHINOSE ,  Satoshi NAKAMURA

Inventor： Kimihiro YAMANAKA ,  Manabu ICHINOSE ,  Satoshi NAKAMURA

IPC: H05K1/16 ,  H05K1/11

CPC classification number: H05K1/116 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/0769 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/0969

Abstract: According to one of the invention, a circuit board comprises a conductive layer. The conductive layer includes a first land portion, a second land portion apart from the first land portion in a plan view, and a line portion connecting the first land portion and the second land portion to each other. The line portion includes lead portions through which a current is to flow and an opening portion arranged between the lead portions. The opening portion penetrates the conductive layer in a thickness direction.

Abstract translation: 根据本发明之一，电路板包括导电层。 导电层包括第一接地部分，在平面图中与第一接地部分分开的第二接地部分和将第一接地部分和第二接地部分彼此连接的线路部分。 线部分包括电流流过的引线部分和布置在引线部分之间的开口部分。 开口部在厚度方向上贯通导电层。

公开(公告)号：US07754599B2

公开(公告)日：2010-07-13

申请号：US12379223

申请日：2009-02-17

Applicant: Yung-Yu Hsu ,  Rong-Chang Feng ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Ji-Cheng Lin ,  Shan-Pu Yu ,  Shou-Lung Chen ,  Chih-Yuan Cheng

Inventor： Yung-Yu Hsu ,  Rong-Chang Feng ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Ji-Cheng Lin ,  Shan-Pu Yu ,  Shou-Lung Chen ,  Chih-Yuan Cheng

IPC: H01L21/44

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/4644 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2201/09909 ,  H01L2924/00

Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.

Abstract translation: 提供一种用于减小通孔应力的结构及其制造方法。 使用栅格结构中的应力块与绝缘材料的主要部分直接接触，具有高的热膨胀系数，使厚度方向上的一个或多个导线或通孔被固定。 因此，由温度加载引起的剪切应力可以被应力块阻挡或吸收。

公开(公告)号：US07745924B2

公开(公告)日：2010-06-29

申请号：US12129889

申请日：2008-05-30

Applicant: Takeshi Shioga ,  Masataka Mizukoshi ,  Kazuaki Kurihara

Inventor： Takeshi Shioga ,  Masataka Mizukoshi ,  Kazuaki Kurihara

IPC: H01L23/485

CPC classification number: H05K1/162 ,  H01G9/025 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0315 ,  Y10S438/957 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).

Abstract translation: 对于用于半导体集成电路元件的电极焊盘，用于信号传输的一些电极焊盘耦合到Ti膜。 用于信号传输的其他电极焊盘通过布线在多层布线中的布线耦合到电极焊盘。 用于电源的电极焊盘耦合到电极焊盘，电极彼此不同的电力线通过布线耦合到电极焊盘。 电极焊盘也耦合到铝箔（阳极）。 用于接地的电极焊盘耦合到接地线通过布线耦合到的电极焊盘。 电极焊盘也耦合到导电聚合物膜（阴极）。

公开(公告)号：US20100118502A1

公开(公告)日：2010-05-13

申请号：US12691154

申请日：2010-01-21

Applicant: Yasushi INAGAKI ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi INAGAKI ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K1/16

CPC classification number: H05K1/115 ,  H01G2/06 ,  H01G4/12 ,  H01G4/224 ,  H01G4/228 ,  H01G4/248 ,  H01G4/40 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/181 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: Chip capacitors are provided in a printed circuit board. In this manner, the distance between an IC chip and each chip capacitor is shortened, and the loop inductance is reduced. In addition, the chip capacitors are accommodated in a core substrate having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Abstract translation: 片状电容器设置在印刷电路板中。 以这种方式，IC芯片和每个芯片电容器之间的距离缩短，并且环路电感减小。 此外，芯片电容器容纳在具有大厚​​度的芯基板中。 因此，印刷电路板的厚度不会变大。

公开(公告)号：US20100115767A1

公开(公告)日：2010-05-13

申请号：US12541267

申请日：2009-08-14

Applicant: Shin-Ping Hsu ,  Chih-Kui Yang

Inventor： Shin-Ping Hsu ,  Chih-Kui Yang

IPC: H05K3/30

CPC classification number: H05K1/162 ,  H05K3/025 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09763 ,  H05K2203/0152 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A method of fabricating a printed circuit board having capacitance components, including: providing a core board having first and second surfaces with first and second wiring layers provided thereon, respectively, and electrically connected, a second dielectric layer, and a carrier board sequentially provided thereon with a second metal layer, a high dielectric material layer, and a third wiring layer with a plurality of first electrode plates thereon; laminating the core board, second dielectric layer, and carrier board to one another; removing the carrier board so as to expose the second metal layer; and patterning the second metal layer so as to form a fifth wiring layer having a plurality of second electrode plates and a plurality of second conductive vias electrically connected to the third wiring layer, thereby allowing the first electrode plates, high dielectric material layer, and second electrode plates together to form a plurality of capacitance components.

Abstract translation: 一种制造具有电容元件的印刷电路板的方法，包括：提供具有分别设置在其上的第一和第二布线层的第一和第二表面的芯板，并且电连接，第二介电层和顺序地设置在其上的载体板 具有第二金属层，高介电材料层和在其上具有多个第一电极板的第三布线层; 将芯板，第二介质层和载体板彼此层叠; 移除载体板以露出第二金属层; 以及图案化所述第二金属层以形成具有多个第二电极板的第五布线层和与所述第三布线层电连接的多个第二导电通孔，从而允许所述第一电极板，高电介质层和第二布线层 电极板一起形成多个电容部件。

公开(公告)号：US20100109142A1

公开(公告)日：2010-05-06

申请号：US12604613

申请日：2009-10-23

Applicant: Chin Hock Toh ,  Yao Huang Huang ,  Ravi Kanth Kolan ,  Wei Liang Yuan ,  Susanto Tanary ,  Yi Sheng Anthony Sun

Inventor： Chin Hock Toh ,  Yao Huang Huang ,  Ravi Kanth Kolan ,  Wei Liang Yuan ,  Susanto Tanary ,  Yi Sheng Anthony Sun

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/10

CPC classification number: H01L21/563 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K3/3478 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09572 ,  H05K2201/10378 ,  H05K2203/043 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.

Abstract translation: 介绍了插件。 插入器包括具有第一和第二表面的插入器基座。 再分配层设置在插入器基座的第一表面上。 插入器具有耦合到再分配层的至少一个插入器焊盘。 它还包括在第二表面上的至少一个中介层接触。 插入器触点通过再分配层电耦合到插入器衬垫。 插入器还包括通过插入器基座的至少一个插入器，用于将插入器触点耦合到再分配层。 插入器通孔包括内插器接触件的回流导电材料。

公开(公告)号：US20100108363A1

公开(公告)日：2010-05-06

申请号：US12582647

申请日：2009-10-20

Applicant: Chih-kuang Yang

Inventor： Chih-kuang Yang

IPC: H01R12/04 ,  H01R43/16

CPC classification number: H05K1/116 ,  H05K1/0393 ,  H05K1/115 ,  H05K3/048 ,  H05K3/4076 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09645 ,  H05K2201/09827 ,  Y10T29/49204

Abstract: Disclosed is a via structure in a multi-layer substrate, comprising a first metal layer, a dielectric layer and a second metal layer. The first metal layer has an upper surface. The dielectric layer covers the first metal layer in which a via is opened to expose the upper surface. The second metal layer is formed in the via and contacts an upper surface and an inclined wall of the via. A contacting surface of the second metal layer has a top line lower than the upper edge of the inclined wall. Alternatively, the second metal layer can be formed on the dielectric layer as being a metal line simultaneously as formed in the via as being a pad. The metal line and the pad are connected electronically. The aforesaid metal second layer can be formed in the via and on the dielectric layer by a metal lift-off process.

Abstract translation: 公开了一种多层基板中的通孔结构，包括第一金属层，电介质层和第二金属层。 第一金属层具有上表面。 电介质层覆盖第一金属层，其中通孔被打开以暴露上表面。 第二金属层形成在通孔中并与通孔的上表面和倾斜壁接触。 第二金属层的接触表面具有比倾斜壁的上边缘低的顶线。 或者，第二金属层可以作为金属线形成在电介质层上，同时形成在通孔中作为焊盘。 金属线和焊盘以电子方式连接。 上述金属第二层可以通过金属剥离工艺在通孔和电介质层上形成。