公开(公告)号：US20150151328A1

公开(公告)日：2015-06-04

申请号：US14554971

申请日：2014-11-26

Applicant: Robert Bosch GmbH

Inventor： Heribert WEBER ,  Yvonne BERGMANN ,  Klaus KRUEGER ,  Andreas RATHJEN

IPC: B05D5/00 ,  B41J2/14

CPC classification number: H01B1/22 ,  C09D11/322 ,  C09D11/52 ,  H01L21/283 ,  H01L21/288 ,  H01L21/76898 ,  H01L2224/24145 ,  H01L2224/48091 ,  H01L2924/00014 ,  H05K1/097 ,  H05K3/1241 ,  H05K3/125 ,  H05K3/403 ,  H05K3/4053 ,  H05K2201/0266 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2203/1105 ,  H01L2224/45099

Abstract: A dispersion is provided having a dispersion medium and a plurality of colloid particles finely distributed in the dispersion medium, the colloid particles being electrically conductive, the dispersion being a functional ink for the wetting of an inner wall of a contacting opening of a substrate using a print process.

Abstract translation: 提供了具有分散介质和细分散在分散介质中的多个胶体颗粒的分散体，胶体颗粒是导电的，该分散体是用于润湿基材的接触开口的内壁的功能油墨，其使用 打印过程。

公开(公告)号：US20150061124A1

公开(公告)日：2015-03-05

申请号：US14523556

申请日：2014-10-24

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/48 ,  H01L21/768 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract translation: 半导体器件具有形成在半导体晶片的有源表面上的保护层。 具有预先施加的保护层的半导体管芯从半导体晶片移动并安装在载体上。 载体上的半导体管芯和接触焊盘被封装。 载体被移除。 在预先施加的保护层和接触垫上形成第一绝缘层。 在第一绝缘层和预先施加的保护层中形成通孔以暴露半导体管芯上的互连部位。 在第一绝缘层上形成互连结构，与半导体管芯和接触焊盘上的互连部位电接触。 互连结构具有形成在第一绝缘层上的再分布层，形成在再分配层上的第二绝缘层和形成在与再分布层电接触的第二电介质上的凸块下金属化层。

公开(公告)号：US08966746B2

公开(公告)日：2015-03-03

申请号：US13064847

申请日：2011-04-20

Applicant: Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

Inventor： Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

IPC: H05K3/30 ,  H05K1/16 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/162 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09563 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of fabricating a cavity capacitor embedded in a printed circuit board including two conductive layers to be used as a power layer and a ground layer, respectively, and a first dielectric layer, placed between the two conductive layers, the method including: removing an upper conductive layer and the first dielectric layer excluding a lower conductive layer of the two conductive layers to allow a cavity to be formed between the two conductive layers, the lower conductive layer being supposed to be used as any one of electrodes of the cavity capacitor; stacking a dielectric material on the cavity to allow a second dielectric layer having a lower stepped portion than the first dielectric layer to be formed in the cavity; and stacking a conductive material on an upper part of the second dielectric layer and side parts of the cavity to allow the upper conductive layer to be used as the other electrode of the cavity capacitor.

Abstract translation: 一种嵌入在印刷电路板中的空腔电容器的方法，包括分别用作功率层和接地层的两个导电层和放置在两个导电层之间的第一介电层，所述方法包括： 上导电层和除了两个导电层的下导电层之外的第一电介质层，以允许在两个导电层之间形成腔，下导电层假定用作空腔电容器的任一电极; 在所述空腔上堆叠电介质材料以允许在所述空腔中形成具有比所述第一电介质层更低的台阶部分的第二电介质层; 并且在第二电介质层的上部和空腔的侧部上堆叠导电材料，以允许上部导电层用作空腔电容器的另一个电极。

公开(公告)号：US08943685B2

公开(公告)日：2015-02-03

申请号：US12923992

申请日：2010-10-19

Applicant: Young Do Kweon ,  Sung Yi ,  Hong-Won Kim

Inventor： Young Do Kweon ,  Sung Yi ,  Hong-Won Kim

IPC: H05K3/02 ,  H05K1/16 ,  H05K3/06 ,  H05K3/46

CPC classification number: H05K1/162 ,  H05K3/062 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09881 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method of manufacturing a capacitor-embedded printed circuit board using a first conductive layer formed on one side of an insulation layer, the method including: forming a second conductive layer on one side of the first conductive layer; forming a second electrode by removing a portion of the second conductive layer; forming a first electrode by removing a portion of the first conductive layer in correspondence with the second electrode; and forming a dielectric layer on one side of the second electrode.

Abstract translation: 一种使用形成在绝缘层的一侧上的第一导电层制造电容器嵌入式印刷电路板的方法，所述方法包括：在所述第一导电层的一侧上形成第二导电层; 通过去除所述第二导电层的一部分来形成第二电极; 通过与所述第二电极对应地移除所述第一导电层的一部分来形成第一电极; 以及在所述第二电极的一侧上形成介电层。

公开(公告)号：US20150000970A1

公开(公告)日：2015-01-01

申请号：US14317538

申请日：2014-06-27

Applicant: KYOCERA SLC Technologies Corporation

Inventor： Masakazu IINO ,  Teruya FUJISAKI ,  Takafumi OYOSHI

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H01L2224/16225 ,  H01L2924/15313 ,  H05K1/113 ,  H05K1/181 ,  H05K3/4069 ,  H05K2201/09509 ,  H05K2201/09618 ,  H05K2201/10734

Abstract: A wiring board includes an insulating layer having a lower layer conductor on a lower surface thereof, a plurality of semiconductor element connection pads arranged in a lattice pattern in a semiconductor element mounting portion 1a having a quadrangular shape on the insulating layer, a via hole formed in the insulating layer below each of the semiconductor element connection pads, and a via conductor filled in the via hole and formed integrally with each of the semiconductor element connection pads. The wiring board includes a reinforcing via hole formed in the insulating layer in an outer region outside an arrangement region of the semiconductor element connection pads in corner portions of the semiconductor element mounting portion, and a reinforcing via conductor formed in the reinforcing via hole.

Abstract translation: 布线基板包括在其下表面具有下层导体的绝缘层，在绝缘层上具有四边形形状的半导体元件安装部分1a中以格子状布置的多个半导体元件连接焊盘，形成通孔 在每个半导体元件连接焊盘之下的绝缘层中，以及填充在通孔中并与每个半导体元件连接焊盘一体形成的通孔导体。 布线基板包括形成在半导体元件安装部的角部的半导体元件连接焊盘的配置区域的外侧的外部区域的绝缘层中的增强通孔，以及形成在加强型通孔中的加强型通路导体。

公开(公告)号：US08846454B2

公开(公告)日：2014-09-30

申请号：US13555531

申请日：2012-07-23

Applicant: Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

Inventor： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L21/44 ,  H01L21/48 ,  H05K1/18 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L25/16 ,  H01L25/10 ,  H01L23/50 ,  H05K3/46

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract translation: 半导体器件具有形成在半导体晶片的有源表面上的保护层。 具有预先施加的保护层的半导体管芯从半导体晶片移动并安装在载体上。 载体上的半导体管芯和接触焊盘被封装。 载体被移除。 在预先施加的保护层和接触垫上形成第一绝缘层。 在第一绝缘层和预先施加的保护层中形成通孔以暴露半导体管芯上的互连部位。 在第一绝缘层上形成互连结构，与半导体管芯和接触焊盘上的互连部位电接触。 互连结构具有形成在第一绝缘层上的再分布层，形成在再分配层上的第二绝缘层和形成在与再分布层电接触的第二电介质上的凸块下金属化层。

公开(公告)号：US08842440B2

公开(公告)日：2014-09-23

申请号：US13930617

申请日：2013-06-28

Applicant: Ibiden Co., Ltd.

Inventor： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing a printed circuit board includes forming an opening portion in a substrate, positioning chip capacitors in the opening portion of the substrate such that the chip capacitors are accommodated in the opening portion of the substrate, forming a buildup structure including an interlayer resin insulating layer and a conductive layer over a surface of the substrate and the chip capacitors accommodated in the opening portion of the substrate, and forming on a surface of the buildup structure bump structures positioned to mount an IC chip such that the chip capacitors in the opening portion of the substrate are positioned directly below the IC chip.

Abstract translation: 一种印刷电路板的制造方法，其特征在于，在基板上形成开口部，将所述基板的开口部中的芯片电容器定位，使得所述芯片电容器容纳在所述基板的开口部，形成包含层间树脂 绝缘层和在基板的表面上的导电层和容纳在基板的开口部分中的芯片电容器，并且在构成堆积结构的凸起结构的表面上形成，以便安装IC芯片，使得开口中的芯片电容器 基板的一部分直接位于IC芯片的正下方。

公开(公告)号：US08822839B2

公开(公告)日：2014-09-02

申请号：US13307213

申请日：2011-11-30

Applicant: Yogo Kawasaki ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

Inventor： Yogo Kawasaki ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

IPC: H05K1/11

CPC classification number: H05K1/113 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/3457 ,  H05K3/381 ,  H05K3/382 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0796 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board including a core substrate, lower interlayer resin insulating layers formed on the surfaces of the core substrate, respectively, through-hole conductors formed in penetrating holes penetrating through the core substrate and the lower interlayer resin insulating layers, conductor circuits formed on the lower interlayer resin insulating layers, respectively, upper interlayer resin insulating layers formed on the conductor circuits and the lower interlayer resin insulating layers, respectively and via hole conductors formed in the upper interlayer resin insulating layers and positioned on the through-hole conductors, respectively.

Abstract translation: 一种多层印刷电路板，包括芯基板，分别形成在芯基板的表面上的下层层间树脂绝缘层，形成在穿透芯基板的穿透孔中的通孔导体和下层间树脂绝缘层，导体 形成在下层树脂绝缘层上的电路分别形成在导体电路和下层间树脂绝缘层上的上层间树脂绝缘层和分别形成在上层间树脂绝缘层中并位于通孔上的通孔导体 导体。

公开(公告)号：US08819933B2

公开(公告)日：2014-09-02

申请号：US12957431

申请日：2010-12-01

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: H01R43/02

CPC classification number: H01L24/10 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/112 ,  H05K2201/0769 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/0979 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49179 ,  H01L2924/00

Abstract: A method for forming an electrical structure. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.

Abstract translation: 一种形成电结构的方法。 电结构包括互连结构和衬底。 衬底包括导电焊盘和电连接到导电焊盘的多个导线迹线。 导电焊盘电连接和机械连接到互连结构。 多条导线包括第一线迹线，第二线迹线，第三线迹线和第四线迹线。 第一线迹和第二线迹均电连接到导电垫的第一侧。 第三线迹电连接到导电垫的第二侧。 第四线迹电连接到所述第一导电焊盘的第三侧。 多个导线配置成分布电流。

公开(公告)号：US08717772B2

公开(公告)日：2014-05-06

申请号：US12566776

申请日：2009-09-25

Applicant: Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed circuit board includes a core substrate having an opening portion, an electronic component provided in the opening portion of the core substrate and including a dielectric body, a first electrode formed over the dielectric body, and a second electrode formed over the dielectric body such that the dielectric body is interposed between the first electrode and the second electrode, and a resin filling a gap between the core substrate and the electronic component in the opening portion of the core substrate. The resin filling the gap includes a filler.

Abstract translation: 印刷电路板包括具有开口部分的芯基板，设置在芯基板的开口部分中的电子部件，包括电介质体，形成在绝缘体上的第一电极和形成在电介质体上的第二电极， 介电体插入在第一电极和第二电极之间，以及树脂填充芯基板的开口部分中的芯基板和电子部件之间的间隙。 填充间隙的树脂包括填料。