公开(公告)号：US20090290316A1

公开(公告)日：2009-11-26

申请号：US11917418

申请日：2006-06-13

Applicant: Takashi Kariya

Inventor： Takashi Kariya

IPC: H05K1/18

CPC classification number: H05K1/11 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A printed wiring board includes a mounting portion on which a dual core processor including two processor cores in a single chip can be mounted, power supply lines, ground lines, and a first layered capacitor and a second layered capacitor that are independently provided for each of the processor cores, respectively. Accordingly, even when the electric potentials of the processor cores instantaneously drop, an instantaneous drop of the electric potential can be suppressed by action of the layered capacitors corresponding to the processor cores, respectively. In addition, even when the voltage of one of the processor cores varies, the variation in the voltage does not affect the other processor core, and thus malfunctioning does not occur.

Abstract translation: 一种印刷线路板包括：安装部，在该安装部上可以搭载有单个芯片的两个处理器芯的双芯处理器，电源线，接地线以及第一分层电容器和第二分层电容器， 处理器核心。 因此，即使当处理器核心的电位瞬时下降时，也可以通过分别对应于处理器核心的分层电容器的作用来抑制电位的瞬时下降。 此外，即使处理器核心中的一个的电压变化，电压的变化也不影响其他的处理器核心，因此不会发生故障。

公开(公告)号：US20090242255A1

公开(公告)日：2009-10-01

申请号：US12369115

申请日：2009-02-11

Applicant: Hirotaka TANIGUCHI ,  Toshiki Furutani ,  Takeshi Furusawa ,  Takashi Kariya

Inventor： Hirotaka TANIGUCHI ,  Toshiki Furutani ,  Takeshi Furusawa ,  Takashi Kariya

IPC: H05K1/16 ,  H01R43/00

CPC classification number: H05K1/187 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3135 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K3/205 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49139 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of manufacturing a wiring board with a built-in electronic component includes providing a first base material comprising a support body and a first metal foil detachably adhered on the support body, forming a connection terminal for mounting an electronic component on the first metal foil of the first base material by an additive method, electrically connecting an electronic component and the connection terminal by arranging the electronic component on the first base material such that a surface of the electronic component on which a circuit is formed faces a surface on which the connection terminal is formed, covering the electronic component with an insulative material after the mounting, and detaching the support body and the first metal foil.

Abstract translation: 制造具有内置电子部件的布线基板的方法包括：提供包括支撑体的第一基材和可拆卸地粘附在所述支撑体上的第一金属箔，形成用于将电子部件安装在所述第一金属箔上的连接端子 的第一基材的第一基材的表面，通过将电子部件布置在第一基材上，使得电子部件的形成有电路的表面面对连接到第一基材的表面， 端子形成，在安装之后用绝缘材料覆盖电子部件，并且分离支撑体和第一金属箔。

公开(公告)号：US20090225525A1

公开(公告)日：2009-09-10

申请号：US12466940

申请日：2009-05-15

Applicant: Yasuhiko Mano ,  Takashi Kariya ,  Shinobu Kato

Inventor： Yasuhiko Mano ,  Takashi Kariya ,  Shinobu Kato

IPC: H05K7/00

CPC classification number: H05K3/4046 ,  H01F17/0006 ,  H01F17/06 ,  H01F41/046 ,  H01F2017/002 ,  H01F2017/065 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0233 ,  H05K1/115 ,  H05K1/185 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/086 ,  H05K2201/09581 ,  Y10T29/4902 ,  H01L2224/05599

Abstract: An inductor embedded in a printed wiring board includes a conductor extending in the thickness direction of a printed circuit board and a magnetic body that is in contact with the conductor with no gap therebetween. For example, the magnetic body is composed of ferrite having a cylindrical tubular shape. The conductor is composed of a copper film formed by plating on an inner peripheral surface of the cylindrical tubular ferrite. The inductor is inserted in the thickness direction of the printed wiring board.

公开(公告)号：US20090159327A1

公开(公告)日：2009-06-25

申请号：US12389456

申请日：2009-02-20

Applicant: Naohiro Hirose ,  Takashi Kariya ,  Yoji Mori

Inventor： Naohiro Hirose ,  Takashi Kariya ,  Yoji Mori

IPC: H05K1/11 ,  H05K1/00

CPC classification number: H01R9/09 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/0256 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K3/184 ,  H05K3/241 ,  H05K3/382 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2203/0594 ,  Y10T29/49155 ,  Y10T29/49194 ,  Y10T428/31504

Abstract: A printed wiring board including a core substrate, a build-up layer formed over the core substrate and including a first insulating layer, a conductor layer formed over the first insulating layer, and a second insulating layer formed over the conductor layer, and one or more wiring patterns formed over the first insulating layer. The conductor layer includes conductor portions, and the conductor portions have notched portions, respectively, facing each other across the wiring pattern.

Abstract translation: 一种印刷电路板，包括芯基板，形成在所述芯基板上并包括第一绝缘层的堆积层，形成在所述第一绝缘层上的导体层和形成在所述导体层上的第二绝缘层，以及一个或 在第一绝缘层上形成更多的布线图案。 导体层包括导体部分，并且导体部分分别具有跨越布线图案彼此面对的切口部分。

公开(公告)号：US20080007925A1

公开(公告)日：2008-01-10

申请号：US11482793

申请日：2006-07-10

Applicant: Takashi Kariya ,  Yasuhiko Mano ,  Shuichi Kawano ,  Liyi Chen

Inventor： Takashi Kariya ,  Yasuhiko Mano ,  Shuichi Kawano ,  Liyi Chen

IPC: H05K7/00

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/16152 ,  H01L2924/207 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/0002 ,  H01L2224/0401 ,  H01L2924/01005

Abstract: This invention provides a small package board integrated with power supply capable of supplying a low level of voltage and high level of current to an IC while achieving a low height of its power supply. It becomes hard to saturate an inductor magnetically when the surface of a copper wire is coated with a magnetic layer, and the inductor can accordingly be provided with a sufficient degree of inductance. A multiplicity of inductors can be provided within a confined space by arranging a multiplicity of inductors in parallel, and by fixing them with resin so as to form an inductor array, thereby making it possible to divide a power supply. The number of power supply lines is increased by dividing the power supply so as to reduce the level of current in an individual power supply line, so that a high level of current can be supplied to an IC chip. Further, a distance between a power supply and the IC chip can be decreased by incorporating a power supply module into the package board so as to reduce generation of heat and curb a drop in voltage in the power supply line, thereby making it possible to supply a high level of current to the IC chip.

Abstract translation: 本发明提供了一种与电源集成的小封装板，其能够在实现其电源的低高度的同时向IC提供低电平和高电平的电流。 当铜线的表面涂覆有磁性层时，磁感应器难以饱和，并且电感器因此可以具有足够的电感。 通过并排布置多个电感器，并且通过用树脂固定它们以形成电感器阵列，可以在限制空间内提供多个电感器，从而可以划分电源。 通过分割电源来增加电源线的数量，以便降低单个电源线中的电流水平，从而可以向IC芯片提供高电平的电流。 此外，通过将电源模块并入封装板中可以减小电源和IC芯片之间的距离，以减少热量的产生并且抑制电源线中的电压下降，从而可以供应 电流高达IC芯片。

公开(公告)号：US20070257761A1

公开(公告)日：2007-11-08

申请号：US11429157

申请日：2006-05-08

Applicant: Yasuhiko Mano ,  Takashi Kariya ,  Shinobu Kato

Inventor： Yasuhiko Mano ,  Takashi Kariya ,  Shinobu Kato

IPC: H01F5/00

CPC classification number: H05K3/4046 ,  H01F17/0006 ,  H01F17/06 ,  H01F41/046 ,  H01F2017/002 ,  H01F2017/065 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0233 ,  H05K1/115 ,  H05K1/185 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/086 ,  H05K2201/09581 ,  Y10T29/4902 ,  H01L2224/05599

Abstract: An inductor embedded in a printed wiring board includes a conductor extending in the thickness direction of a printed circuit board and a magnetic body that is in contact with the conductor with no gap therebetween. For example, the magnetic body is composed of ferrite having a cylindrical tubular shape. The conductor is composed of a copper film formed by plating on an inner peripheral surface of the cylindrical tubular ferrite. The inductor is inserted in the thickness direction of the printed wiring board.

Abstract translation: 嵌入印刷电路板的电感器包括沿着印刷电路板的厚度方向延伸的导体和与导体接触而不间隙的磁体。 例如，磁性体由具有圆柱形管状的铁氧体构成。 导体由在圆筒形管状铁氧体的内周面上电镀形成的铜膜构成。 电感器沿印刷电路板的厚度方向插入。

公开(公告)号：US20070227765A1

公开(公告)日：2007-10-04

申请号：US11757750

申请日：2007-06-04

Applicant: Hajime SAKAMOTO ,  Tadashi Sugiyama ,  Dongdong Wang ,  Takashi Kariya

Inventor： Hajime SAKAMOTO ,  Tadashi Sugiyama ,  Dongdong Wang ,  Takashi Kariya

IPC: H05K1/16

CPC classification number: H01L24/29 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/83 ,  H01L25/03 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/18162 ,  H01L2924/30107 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09918 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A multilayer printed circuit board has an IC chip 20 included in a core substrate 30 in advance and a transition layer 38 provided on a pad 24 of the IC chip 20. Due to this, it is possible to electronically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on the die pad 24, it is possible to prevent resin residues on the pad 24 and to improve connection characteristics between the pad 24 and a via hole 60 and reliability.

Abstract translation: 多层印刷电路板预先包括在芯基板30中的IC芯片20和设置在IC芯片20的焊盘24上的过渡层38。 由此，可以在不使用引线部件和密封树脂的情况下将IC芯片电连接到多层印刷电路板。 此外，通过在芯片焊盘24上设置由铜制成的过渡层38，可以防止焊盘24上的树脂残留，并且改善焊盘24和通孔60之间的连接特性以及可靠性。

公开(公告)号：US07262975B2

公开(公告)日：2007-08-28

申请号：US11443046

申请日：2006-05-31

Applicant: Takashi Kariya ,  Toshiki Furutani

Inventor： Takashi Kariya ,  Toshiki Furutani

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0271 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49151 ,  Y10T29/49162 ,  H01L2224/0401

Abstract: A multilayer printed wiring board 10 includes: a build-up layer 30 that is formed on a core substrate 20 and has a conductor pattern 32 disposed on an upper surface; a low elastic modulus layer 40 that is formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a IC chip 70; and conductor posts 50 that pass through the low elastic modulus layer 40 and electrically connect lands 52 with conductor patterns 32. The conductor posts 50 have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 μm, and the aspect ratio Rasp of external conductor posts 50a, which are positioned at external portions of the low elastic modulus layer 40, is greater than or equal to the aspect ratio Rasp of internal conductor posts 50b, which are positioned at internal portions of the low elastic modulus layer 40.

Abstract translation: 多层印刷布线板10包括：形成在芯基板20上并具有布置在上表面上的导体图案32的堆积层30; 形成在积层30上的低弹性模量层40; 焊盘52设置在低弹性模量层40的上表面上并通过焊料凸块66连接到IC芯片70; 以及穿过低弹性模量层40并将焊盘52与导体图案32电连接的导体柱50.导体柱50的纵横比Rasp（高度/最小直径）不小于4，最小直径超过30μm ，并且位于低弹性模量层40的外部的外部导体柱50a的纵横比Rasp大于或等于位于内部部分的内部导体柱50b的纵横比Rasp 的低弹性模量层40。

公开(公告)号：US20070134910A1

公开(公告)日：2007-06-14

申请号：US11580927

申请日：2006-10-16

Applicant: Takashi Kariya ,  Hironori Tanaka

Inventor： Takashi Kariya ,  Hironori Tanaka

IPC: H01L21/4763

CPC classification number: H05K1/162 ,  H01L21/4867 ,  H01L23/498 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/388 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A high-dielectric sheet for a printed circuit board includes a first electrode, a first sputter film formed on the first electrode, an intermediate layer formed on the first sputter film by calcining a sol-gel film, a second sputter film formed on the intermediate layer, and a second electrode provided on the second sputter film.

Abstract translation: 用于印刷电路板的高电介质片包括第一电极，形成在第一电极上的第一溅射膜，通过煅烧溶胶 - 凝胶膜在第一溅射膜上形成的中间层，形成在中间体上的第二溅射膜 层和设置在第二溅射膜上的第二电极。

公开(公告)号：US20060245139A1

公开(公告)日：2006-11-02

申请号：US11341485

申请日：2006-01-30

Applicant: Takashi Kariya

Inventor： Takashi Kariya

IPC: H01G4/255

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2203/0152 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: When a package substrate with a built-in capacitor includes a first thin-film small electrode 41aa and a second thin-film small electrode 42aa that are electrically short-circuited to each other via a pinhole P in a high-dielectric layer 43, a power supply post 61a and a via hole 61b are not formed in the first thin-film small electrode 41aa, and a ground post 62a and a via hole 62b are not formed in the second thin-film small electrode 42aa, either. As a result, the short-circuited small electrodes 41aa and 42aa are electrically connected to neither a power supply line nor a ground line, and become a potential independent from a power supply potential and a ground potential. Therefore, in the thin-film capacitor 40, only the portion where the short-circuited small electrodes 41aa and 42aa sandwich the high dielectric layer 43 loses the capacitor function, and portions where other thin-film small electrodes 41a and 42a sandwich the high dielectric layer 43 maintain the capacitor function.

Abstract translation: 当具有内置电容器的封装衬底包括通过高电介质层43中的针孔P彼此电短路的第一薄膜小电极41aa和第二薄膜小电极42aa时， 在第一薄膜小电极41a中没有形成供电支柱61a和通孔61b，并且在第二薄膜小电极42中没有形成接地柱62a和通孔62b 也可以。 结果，短路的小电极41aa和42aa既不与电源线也不与接地线电连接，并且成为独立于电源电位和接地电位的电位。 因此，在薄膜电容器40中，只有短路的小电极41aa和42aa夹在高电介质层43的部分失去电容器功能，其他薄膜小电极41a和42a的部分 夹住高介电层43保持电容器的功能。