公开(公告)号：US20170278805A1

公开(公告)日：2017-09-28

申请号：US15442207

申请日：2017-02-24

申请人： Synaptics Japan GK

发明人： Atsushi OBUCHI ,  Takashi YONEOKA ,  Hiroshi KAGA

IPC分类号： H01L23/58 ,  H01L23/482 ,  H01L21/78 ,  H01L23/00 ,  H01L23/485 ,  H01L21/66

CPC分类号： H01L23/585 ,  H01L21/78 ,  H01L22/32 ,  H01L23/4827 ,  H01L23/485 ,  H01L23/564 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02141 ,  H01L2224/0215 ,  H01L2224/02181 ,  H01L2224/0219 ,  H01L2224/02251 ,  H01L2224/0226 ,  H01L2224/03826 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13144 ,  H01L2924/04941

摘要： A large scale integrated circuit chip includes a semiconductor circuit having a multilayered wiring structure, a metal guard ring surrounding the semiconductor circuit, and a plurality of external connection terminals, on a semiconductor circuit. The plurality of external connection terminals connect to an uppermost-layer wiring of the multilayered wiring structure and are exposed on a surface of the large scale integrated circuit chip. A predetermined external connection terminal conducts to a predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring. One side of the external connection terminal extending over the guard ring connects to the conductive piece, and the other side of the external connection terminal connects to the uppermost-layer wiring within the guard ring. Thus, a cutout part is not necessary in the guard ring.

公开(公告)号：US09601460B2

公开(公告)日：2017-03-21

申请号：US14618413

申请日：2015-02-10

申请人： XINTEC INC.

发明人： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chia-Ming Cheng ,  Shu-Ming Chang ,  Tzu-Wen Tseng

IPC分类号： H01L23/06 ,  H01L23/00 ,  H01L23/31 ,  H01L29/06 ,  H01L23/525

CPC分类号： H01L24/94 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/0657 ,  H01L2224/0224 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/06165 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/94 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0665

摘要： A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess.

公开(公告)号：US20160181210A1

公开(公告)日：2016-06-23

申请号：US15059278

申请日：2016-03-02

申请人： ROHM CO., LTD.

发明人： Osamu MIYATA ,  Masaki KASAI ,  Shingo HIGUCHI

IPC分类号： H01L23/00 ,  H01L23/544

CPC分类号： H01L23/3178 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/528 ,  H01L23/544 ,  H01L23/562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2223/5446 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2924/00012

摘要： An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip, a groove formed in a periphery of a surface of the semiconductor chip being tapered toward a rear surface of the semiconductor chip, wherein the sealing resin layer is partly disposed in the groove.

摘要翻译： 本发明的半导体器件包括具有钝化膜的半导体芯片和设置在钝化膜上方的用于密封半导体芯片的前侧的密封树脂层，形成在半导体芯片的表面的周边的槽朝向 半导体芯片的后表面，其中密封树脂层部分地设置在凹槽中。

公开(公告)号：US20160111352A1

公开(公告)日：2016-04-21

申请号：US14967965

申请日：2015-12-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Daniel J. Couture ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02125 ,  H01L2224/0226 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/05442

摘要： An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one portion of the patterned second dielectric layer is over the location of the void area of the topographical semiconductor feature. A first metal layer is deposited over the second dielectric layer, at least one portion of the first dielectric layer, and a portion of the top surface of the topographical semiconductor feature. A chemical mechanical polish of the first metal layer is performed, wherein the chemical mechanical polish reaches the top surface of at least one of the one or more portions of the second dielectric layer.

摘要翻译： 在空隙区域上形成用于介电层的半导体结构的方法包括确定形貌半导体特征的空隙区域的位置。 第二电介质层沉积在第一介电层和地形半导体特征的顶表面上。 将第二介电层图案化成一个或多个部分，其中图案化的第二介电层的至少一部分在形貌半导体特征的空隙区域的位置之上。 第一金属层沉积在第二电介质层上，第一介电层的至少一部分和形貌半导体特征的顶表面的一部分。 执行第一金属层的化学机械抛光，其中化学机械抛光剂到达第二介电层的一个或多个部分中的至少一个的顶表面。

公开(公告)号：US09312228B2

公开(公告)日：2016-04-12

申请号：US14795955

申请日：2015-07-10

申请人： ROHM CO., LTD.

发明人： Osamu Miyata ,  Masaki Kasai ,  Shingo Higuchi

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L23/528

CPC分类号： H01L23/3178 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/528 ,  H01L23/544 ,  H01L23/562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2223/5446 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2924/00012

摘要： An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.

公开(公告)号：US20160064348A1

公开(公告)日：2016-03-03

申请号：US14470765

申请日：2014-08-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo Lung Pan ,  Yu-Feng Chen ,  Chen-Shien Chen

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/147 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02245 ,  H01L2224/02251 ,  H01L2224/0226 ,  H01L2224/10175 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13687 ,  H01L2224/1411 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/0541 ,  H01L2924/014 ,  H01L2924/00014

摘要： Packaging devices, packaged semiconductor devices, and packaging methods are disclosed. In some embodiments, a packaging device includes a substrate having an integrated circuit die mounting region disposed thereon. Microstructures are disposed proximate a side of the integrated circuit die mounting region of the substrate.

摘要翻译： 公开了包装设备，封装半导体器件和封装方法。 在一些实施例中，包装装置包括其上设置有集成电路管芯安装区域的基板。 微结构设置在基板的集成电路管芯安装区域的一侧附近。

公开(公告)号：US09209140B2

公开(公告)日：2015-12-08

申请号：US14015808

申请日：2013-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Feng Chen ,  Kai-Chiang Wu ,  Chun-Lin Lu ,  Hung-Jui Kuo

IPC分类号： H01L23/58 ,  H01L23/498 ,  H01L23/00 ,  H01L23/16 ,  H01L23/544 ,  H01L23/10 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/48 ,  H01L23/14 ,  H01L21/48 ,  H01L21/768

CPC分类号： H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/34 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/10 ,  H01L23/147 ,  H01L23/16 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/4334 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2021/6024 ,  H01L2223/5446 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/11318 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads are arranged in a ball grid array (BGA), and the BGA includes a plurality of corners. A metal dam is disposed around each of the plurality of corners of the BGA.

摘要翻译： 公开了半导体器件及其制造方法。 在一些实施例中，半导体器件包括衬底以及设置在衬底上的多个接触焊盘。 接触垫布置成球栅阵列（BGA），并且BGA包括多个拐角。 在BGA的多个拐角的每一个周围设置一个金属坝。

公开(公告)号：US09111819B2

公开(公告)日：2015-08-18

申请号：US14565498

申请日：2014-12-10

申请人： ROHM CO., LTD.

发明人： Osamu Miyata ,  Masaki Kasai ,  Shingo Higuchi

IPC分类号： H01L23/29 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/3178 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/528 ,  H01L23/544 ,  H01L23/562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2223/5446 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2924/00012

摘要： An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.

公开(公告)号：US09024431B2

公开(公告)日：2015-05-05

申请号：US12846214

申请日：2010-07-29

申请人： Chung-Shi Liu ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L23/532 ,  H01L23/00

CPC分类号： H01L23/528 ,  H01L23/48 ,  H01L23/481 ,  H01L23/482 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0225 ,  H01L2224/0226 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13018 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/19041 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

摘要翻译： 公开了一种用于形成半导体管芯接触结构的系统和方法。 一个实施例包括顶层金属接触，例如铜，其厚度足够大以充当底层低k，极低k或超低k电介质层的缓冲器。 可以在顶层金属接触件上方形成接触焊盘或后钝化互连，并且可以形成铜柱或焊料凸块以与顶层金属接触件电连接。

公开(公告)号：US08786106B2

公开(公告)日：2014-07-22

申请号：US14059489

申请日：2013-10-22

申请人： Rohm Co., Ltd.

发明人： Osamu Miyata ,  Masaki Kasai ,  Shingo Higuchi

IPC分类号： H01L23/48

CPC分类号： H01L23/3178 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/528 ,  H01L23/544 ,  H01L23/562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2223/5446 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2924/00012

摘要： An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.

摘要翻译： 本发明的半导体器件包括具有钝化膜的半导体芯片和设置在钝化膜上方的密封树脂层，用于密封半导体芯片的正面。 密封树脂层延伸到钝化膜的侧表面以覆盖侧表面。