公开(公告)号：US20140264835A1

公开(公告)日：2014-09-18

申请号：US13831964

申请日：2013-03-15

申请人： UNITED TEST AND ASSEMBLY CENTER LTD.

发明人： Chuen Khiang WANG

IPC分类号： H01L23/498 ,  H01L21/768 ,  H05K1/02

CPC分类号： H01L23/5384 ,  H01L21/4832 ,  H01L21/56 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/09 ,  H05K1/115 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer.

摘要翻译： 提供封装衬底，半导体封装以及用于形成半导体封装的方法。 封装衬底包括具有第一和第二主表面的基底衬底和延伸穿过基底衬底的第一至第二主表面的多个通孔触头。 具有多个开口的第一导电层设置在基底基板的第一表面上并经由触点。 开口被配置成匹配封装衬底的导电迹线布局。 导电迹线设置在第一导电层上。 导电迹线通过第一导电层的一些开口直接耦合到通孔触点。

公开(公告)号：US20140227832A1

公开(公告)日：2014-08-14

申请号：US14257017

申请日：2014-04-21

申请人： United Test and Assembly Center Ltd.

发明人： Chuen Khiang WANG ,  Nathapong SUTHIWONGSUNTHORN ,  Kriangsak SAE LE ,  Antonio Jr B DIMAANO ,  Catherine Bee Liang NG ,  Richard Te GAN ,  Kian Teng ENG

IPC分类号： H01L21/48 ,  H01L21/56

CPC分类号： H01L23/49861 ,  H01L21/2885 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4832 ,  H01L21/4839 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

摘要翻译： 公开了一种设备。 该装置包括具有第一和第二主表面的载体衬底。 第一表面包括管芯区域和接触焊盘，第二表面包括封装接触。 载体衬底包括图案化引线框架，其将导电迹线和具有通孔触点的通孔级限定在线路电平。 图案化引线框架提供接触焊盘和封装触点之间的互连。 载体衬底还包括隔离导电迹线和通孔触点的电介质层。 该装置包括安装在第一表面的管芯区域上的管芯。

公开(公告)号：US08544755B2

公开(公告)日：2013-10-01

申请号：US13171421

申请日：2011-06-28

申请人： Rahamat Bidin ,  Hao Liu

发明人： Rahamat Bidin ,  Hao Liu

IPC分类号： G06K19/06

CPC分类号： G06K19/07745 ,  H01L23/3121 ,  H01L23/49855 ,  H01L24/45 ,  H01L24/48 ,  H01L2223/6677 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A SIM card is presented. The SIM card includes a support carrier having a first and a second major surface. The support carrier includes a cavity which extends partially into the carrier from the first major surface. The SIM card further includes a chip package disposed within the cavity. The support carrier is sufficiently flexible to bend when the SIM card is being inserted into or removed from a SIM card holder.

摘要翻译： 提供SIM卡。 SIM卡包括具有第一和第二主表面的支撑载体。 支撑载体包括从第一主表面部分地延伸到载体中的空腔。 SIM卡还包括设置在腔内的芯片封装。 当SIM卡被插入或从SIM卡夹持器移除时，支撑托架足够弯曲。

公开(公告)号：US08426246B2

公开(公告)日：2013-04-23

申请号：US13400578

申请日：2012-02-21

申请人： Chin Hock Toh ,  Hao Liu ,  Ravi Kanth Kolan

发明人： Chin Hock Toh ,  Hao Liu ,  Ravi Kanth Kolan

IPC分类号： H01L21/00

CPC分类号： H01L23/481 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.

摘要翻译： 公开了一种包括具有第一和第二主表面的基板的管芯。 模具具有至少一个未填充的穿过基底的主表面的通孔。 未填充的通孔用作排气口以释放组装期间产生的压力。

公开(公告)号：US20120220082A1

公开(公告)日：2012-08-30

申请号：US13467050

申请日：2012-05-09

申请人： Catherine Bee Liang NG ,  Kriangsak Sae LE ,  Chuen Khiang WANG ,  Nathapong SUTHIWONGSUNTHORN

发明人： Catherine Bee Liang NG ,  Kriangsak Sae LE ,  Chuen Khiang WANG ,  Nathapong SUTHIWONGSUNTHORN

IPC分类号： H01L21/56

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48145 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A permanent carrier is provided and the at least one die is attached to the permanent carrier. The first surface of the at least one die is facing the permanent carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The first surface of the cap contacts the permanent carrier and the second surface of the cap is disposed at a different plane than the second surface of the die.

摘要翻译： 公开了半导体封装和形成半导体封装的方法。 该方法包括提供具有第一表面和第二表面的至少一个模具。 管芯的第二表面包括多个导电焊盘。 提供永久性载体并且至少一个管芯附接到永久性载体。 至少一个管芯的第一表面面向永久性载体。 形成具有第一和第二表面的盖以封装至少一个管芯。 盖的第一表面与永久性载体接触，并且盖的第二表面设置在与模具的第二表面不同的平面上。

公开(公告)号：US08247272B2

公开(公告)日：2012-08-21

申请号：US12489409

申请日：2009-06-22

申请人： Yong Chuan Koh ,  Jimmy Siat ,  Jeffrey Nantes Salamat ,  Lope Vallespin Pepito, Jr. ,  Ronaldo Cayetano Calderon ,  Rodel Manalac ,  Pang Hup Ong ,  Kian Teng Eng

发明人： Yong Chuan Koh ,  Jimmy Siat ,  Jeffrey Nantes Salamat ,  Lope Vallespin Pepito, Jr. ,  Ronaldo Cayetano Calderon ,  Rodel Manalac ,  Pang Hup Ong ,  Kian Teng Eng

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48478 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48847 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/78303 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2224/85395 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85447 ,  H01L2225/0651 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19107 ,  H01L2924/2076 ,  H01L2924/00014 ,  H01L2924/01001 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4826 ,  H01L2924/00015 ,  H01L2924/01049 ,  H01L2924/01006

摘要： A semiconductor package and a method for constructing the package are disclosed. The package includes a substrate and a die attached thereto. A first contact region is disposed on the substrate and a second contact region is disposed on the die. The first contact region, for example, comprises copper coated with an OSP material. A copper wire bond electrically couples the first and second contact regions. Wire bonding includes forming a ball bump on the first contact region having a flat top surface. Providing the flat top surface is achieved with a smoothing process. A ball bond is formed on the second contact region, followed by stitching the wire onto the flat top surface of the ball bump on the first contact region.

摘要翻译： 公开了一种用于构造封装的半导体封装和方法。 该包装包括一个基片和一个附着于其上的管芯。 第一接触区域设置在基板上，并且第二接触区域设置在管芯上。 第一接触区域例如包括用OSP材料涂覆的铜。 铜线接合电耦合第一和第二接触区域。 线接合包括在具有平坦顶表面的第一接触区域上形成球凸点。 通过平滑处理实现提供平坦的顶面。 在第二接触区域上形成球接合，然后将线缝合到第一接触区域上的球凸块的平坦顶表面上。

公开(公告)号：US08115292B2

公开(公告)日：2012-02-14

申请号：US12604613

申请日：2009-10-23

申请人： Chin Hock Toh ,  Yao Huang Huang ,  Ravi Kanth Kolan ,  Wei Liang Yuan ,  Susanto Tanary ,  Anthony Yi Sheng Sun

发明人： Chin Hock Toh ,  Yao Huang Huang ,  Ravi Kanth Kolan ,  Wei Liang Yuan ,  Susanto Tanary ,  Anthony Yi Sheng Sun

IPC分类号： H01L23/02

CPC分类号： H01L21/563 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K3/3478 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09572 ,  H05K2201/10378 ,  H05K2203/043 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.

摘要翻译： 介绍了插件。 插入器包括具有第一和第二表面的插入器基座。 再分配层设置在插入器基座的第一表面上。 插入器具有耦合到再分配层的至少一个插入器焊盘。 它还包括在第二表面上的至少一个中介层接触。 插入器触点通过再分配层电耦合到插入器衬垫。 插入器还包括通过插入器基座的至少一个插入器，用于将插入器触点耦合到再分配层。 插入器通孔包括内插器接触件的回流导电材料。

公开(公告)号：US08030768B2

公开(公告)日：2011-10-04

申请号：US12108563

申请日：2008-04-24

申请人： Roel Robles ,  Danny Retuta ,  Mary Annie Cheong ,  Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Richard Gan

发明人： Roel Robles ,  Danny Retuta ,  Mary Annie Cheong ,  Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Richard Gan

IPC分类号： H01L23/488 ,  H01L21/56

CPC分类号： H01L24/16 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/12 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/82039 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections.

摘要翻译： 一种半导体封装，其具有在第一表面上具有凹凸金属化（UBM）的半导体芯片和具有开放通孔的基板。 衬底被附接到半导体芯片，UBM与开放的通孔对准。 密封剂围绕半导体芯片和衬底，并且导体填充开放通孔以形成外部封装连接。

公开(公告)号：US07883938B2

公开(公告)日：2011-02-08

申请号：US12124880

申请日：2008-05-21

申请人： Ravi Kanth Kolan ,  Anthony Sun Yi Sheng ,  Liu Hao ,  Toh Chin Hock

发明人： Ravi Kanth Kolan ,  Anthony Sun Yi Sheng ,  Liu Hao ,  Toh Chin Hock

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

摘要： A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality of open vias; attaching a third silicon wafer to the second silicon wafer, wherein the third silicon wafer has a plurality of open vias, and the open vias of the second and third silicon wafers are aligned with one another; etching a bonding material that attaches the wafers from the aligned open vias; filling the aligned open vias with a conductor; forming conductive bumps at open ends of the aligned open vias; back grinding the first silicon wafer; separating the stacked semiconductor dies from each other; attaching the bump end of the stacked semiconductor dies onto a substrate; encapsulating the stacked semiconductor dies and substrate; and singulating the encapsulated assembly.

摘要翻译： 一种制造多个堆叠管芯半导体封装的方法，包括：将第二硅晶片连接到第一硅晶片，其中所述第二硅晶片具有多个开口; 将第三硅晶片附接到所述第二硅晶片，其中所述第三硅晶片具有多个开放通孔，并且所述第二和第三硅晶片的所述开放通孔彼此对准; 蚀刻从对准的开放通孔连接晶片的接合材料; 用导体填充对齐的开放通孔; 在对齐的开放通孔的开口端形成导电凸块; 背面研磨第一个硅晶片; 将堆叠的半导体管芯彼此分离; 将堆叠的半导体管芯的凸起端附接到基板上; 封装堆叠的半导体管芯和衬底; 并分离封装的组件。

公开(公告)号：US20090146276A1

公开(公告)日：2009-06-11

申请号：US12330681

申请日：2008-12-09

申请人： Saravuth SIRINORAKUL ,  Kasemsan Kongthaworn

发明人： Saravuth SIRINORAKUL ,  Kasemsan Kongthaworn

IPC分类号： H01L23/495

CPC分类号： H01L23/49548 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49572 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A flip-chip leadframe semiconductor package designed to improve mold flow around the leadframe and semiconductor die. An embodiment of the semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulant covering the leadframe and semiconductor die, wherein a portion of the leadframe that is attached to the semiconductor die is below a portion of the leadframe that enters the encapsulant.

摘要翻译： 一种倒装芯片引线框半导体封装，旨在改善引线框和半导体芯片周围的模具流动。 半导体封装的实施例包括引线框架，附接到引线框架的半导体管芯以及覆盖引线框架和半导体管芯的密封剂，其中附接到半导体管芯的引线框架的一部分低于进入的引线框架的一部分 密封剂。