公开(公告)号：US07521812B2

公开(公告)日：2009-04-21

申请号：US11678598

申请日：2007-02-25

申请人： Jin-Yuan Lee ,  Ying-Chih Chen ,  Mou-Shiung Lin

发明人： Jin-Yuan Lee ,  Ying-Chih Chen ,  Mou-Shiung Lin

IPC分类号： H01L23/485 ,  H01L23/49

CPC分类号： H01L24/48 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/45144 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/854 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/04953 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

摘要翻译： 提供了一种方法和结构，以在集成电路管芯上形成的有源和/或无源器件和/或低k电介质上实现引线接合连接。 提供了具有有源和/或无源器件的半导体衬底，其中在有源和/或无源器件上形成互连金属化。 提供了形成在互连金属化之上的钝化层，其中在钝化层中形成开口以形成互连金属化的上金属层。 柔性金属焊盘形成在钝化层上方，其中柔性金属接合焊盘通过开口连接到上金属层，并且其中柔性金属接合焊盘基本上形成在有源和/或无源器件的上方。 顺应性金属接合焊盘可以由复合金属结构形成。

公开(公告)号：US07468316B2

公开(公告)日：2008-12-23

申请号：US11930163

申请日：2007-10-31

申请人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

IPC分类号： H01L21/44

CPC分类号： H01L24/12 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13007 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00

摘要： A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

公开(公告)号：US20080284014A1

公开(公告)日：2008-11-20

申请号：US12045029

申请日：2008-03-10

申请人： Jin-Yuan Lee ,  Hsin-Jung Lo

发明人： Jin-Yuan Lee ,  Hsin-Jung Lo

IPC分类号： H01L23/52

CPC分类号： H01L24/86 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4985 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/02311 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2924/01031 ,  H01L2224/05552 ,  H01L2924/013

摘要： A chip assembly includes a semiconductor chip, a bump and an external circuit. The semiconductor chip includes a semiconductor substrate, a transistor in and on the semiconductor substrate, multiple dielectric layers over the semiconductor substrate, a metallization structure over the semiconductor substrate, wherein the metallization structure is connected to the transistor, and a passivation layer over the metallization structure, over the dielectric layers and over the transistor. The bump is connected to the metallization structure through an opening in the passivation layer, wherein the bump includes an adhesion/barrier layer and a gold layer over the adhesion/barrier layer. The external circuit can be connected to the bump using a tape carrier package (TCP), a chip-on-film (COF) package or a chip-on-glass (COG) assembly.

摘要翻译： 芯片组件包括半导体芯片，凸块和外部电路。 半导体芯片包括半导体衬底，半导体衬底中和晶体管，半导体衬底上的多个电介质层，半导体衬底上的金属化结构，其中金属化结构连接到晶体管，以及金属化之上的钝化层 结构，在电介质层和晶体管上方。 凸块通过钝化层中的开口连接到金属化结构，其中凸块包括粘合/阻挡层和粘附/阻挡层上的金层。 外部电路可以使用载带封装（TCP），片上芯片（COF）封装或玻璃（COG）组件连接到凸块。

公开(公告)号：US07446031B2

公开(公告)日：2008-11-04

申请号：US11927719

申请日：2007-10-30

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L21/4763

CPC分类号： H01L23/60 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/62 ,  H01L24/05 ,  H01L27/0248 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

公开(公告)号：US20080265401A1

公开(公告)日：2008-10-30

申请号：US12172275

申请日：2008-07-14

申请人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

IPC分类号： H01L23/48

CPC分类号： H01L21/6835 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  Y10T29/5313 ,  Y10T29/5317 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

摘要： An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

摘要翻译： 集成芯片封装结构及其制造方法是通过在有机基板上附着模具并在模具和有机基板的顶部形成薄膜电路层。 其中薄膜电路层具有电连接到模具的金属焊盘的外部电路，其延伸到模具的有效表面外部的区域，以扇出模具的金属焊盘。 此外，多个有源器件和内部电路位于管芯的有效表面上。 有源器件的信号通过内部电路传输到外部电路，并通过内部电路从外部电路传输回其他有源器件。 此外，芯片封装结构允许将具有不同功能的多个裸片封装在集成封装中并通过外部电路电连接裸片。

公开(公告)号：US07439626B2

公开(公告)日：2008-10-21

申请号：US11856075

申请日：2007-09-17

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L23/48

CPC分类号： H01L23/60 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/62 ,  H01L24/05 ,  H01L27/0248 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

公开(公告)号：US20080246154A1

公开(公告)日：2008-10-09

申请号：US12138453

申请日：2008-06-13

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L23/52

CPC分类号： H01L21/768 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/60 ,  H01L24/11 ,  H01L24/12 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/10 ,  H01L28/20 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.

摘要翻译： 本发明在完成的半导体晶片的顶部上添加一层或多层厚的聚合物电介质和一层或多层厚的宽金属线，后钝化。 厚的宽金属线路可用于长信号路径，也可用于电源总线或电源平面，时钟分配网络，关键信号和用于倒装芯片应用的I / O焊盘的重新分配。 光刻胶定义的电镀，溅射/蚀刻或双重和三重镶嵌技术用于形成金属线和通孔填充。

公开(公告)号：US20080169024A1

公开(公告)日：2008-07-17

申请号：US11847346

申请日：2007-08-30

申请人： Jin-Yuan Lee

发明人： Jin-Yuan Lee

IPC分类号： H01L31/00

CPC分类号： H01L31/075 ,  H01L31/022425 ,  Y02E10/548

摘要： A photovoltaic device which includes a first type doped single crystal silicon substrate, a second type doped silicon layer, an intrinsic silicon layer, a first metal electrode layer, and a second metal electrode layer. The intrinsic silicon layer is disposed between the first type doped single crystal silicon substrate and the second type doped silicon layer. The thickness of the intrinsic silicon layer is between 10 μm and 100 μm. The first metal electrode layer is disposed on a first surface of the first type doped single crystal silicon substrate away from the intrinsic silicon layer. The second metal electrode layer is disposed on a second surface of the second type doped silicon layer away from the intrinsic silicon layer.

摘要翻译： 一种光电器件，包括第一掺杂单晶硅衬底，第二掺杂硅层，本征硅层，第一金属电极层和第二金属电极层。 本征硅层设置在第一掺杂单晶硅衬底和第二掺杂硅层之间。 本征硅层的厚度在10μm和100μm之间。 第一金属电极层设置在远离本征硅层的第一掺杂单晶硅衬底的第一表面上。 第二金属电极层设置在远离本征硅层的第二种掺杂硅层的第二表面上。

公开(公告)号：US20080099928A1

公开(公告)日：2008-05-01

申请号：US11930210

申请日：2007-10-31

申请人： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

发明人： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC分类号： H01L23/52

CPC分类号： H01L24/12 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0949 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

公开(公告)号：US20080080113A1

公开(公告)日：2008-04-03

申请号：US11864938

申请日：2007-09-29

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Chien-Kang Chou

IPC分类号： H02H9/00

CPC分类号： H01L23/552 ,  H01L21/76816 ,  H01L21/76873 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L27/0251 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48764 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/01039 ,  H01L2924/00 ,  H01L2224/05552

摘要： An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.