摘要:
A method for packaging and testing a semiconductor die is provided. The method includes forming a temporary package for the die that has a size, shape and lead configuration that is the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. In an illustrative embodiment the package is formed in a SOJ configuration. The package includes a base, an interconnect and a force applying mechanism. The package base can be formed of ceramic or plastic using a ceramic lamination process or a Cerdip formation process.
摘要:
An improved interconnect for semiconductor dice, a method for testing dice using the interconnect, and a method for fabricating the interconnect are provided. The interconnect includes dense arrays of contact members configured to establish temporary electrical communication with contact locations on a die under test. In addition, the interconnect includes patterns of multi level conductors formed on different levels of the substrate and separated by insulating layers. The multi level conductors can be formed with a higher density and with less cross talk than planar conductors to permit high speed testing of dice having a large number of bond pads. The interconnect can be configured for use with a temporary package for housing a single die for burn-in or other testing. Electrical paths between terminal contacts on the package and the multi level conductors on the interconnect can be formed by microbump tape having low resistance microbumps bonded to the multi level conductors.
摘要:
A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.
摘要:
A stackable chip scale semiconductor package and a method for fabricating the package are provided. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second contacts formed on an opposing second surface of the substrate. Conductive vias in the substrate electrically connect the first contacts to the second contacts. In addition, the first contacts and the second contacts have a mating configuration, such that a second package can be stacked on and electrically connected to the package. The method for fabricating the package includes the steps of: laser machining and etching the vias, forming an insulating layer in the vias, and then depositing a conductive material within the vias.
摘要:
A method for packaging a bare semiconductor die using a one piece package body with a pattern of external conductors is provided. The package body includes a die mounting location and an interconnect opening that aligns with the bond pads on the die. Electrical interconnects, such as wire bonds, are formed through the interconnect opening to establish electrical communication between the bond pads on the die and the conductors on the package body. The conductors on the package body can include solder bumps to permit the package to be flip chip mounted to a supporting substrate such as a printed circuit board or to be mounted in a chip-on-board configuration. The package can be fabricated by bulk micro-machining silicon wafers to form the package bodies, attaching the dice to the package bodies, and then singulating the wafer. Alternately the package body can be formed of a FR-4 material. In addition, multiple dice can be attached to a package body to form a multi-chip module.
摘要:
A method for forming contact pins adapted to form an electrical connection with a mating contact location is provided. In a first embodiment, the contact pins are formed on an interconnect used for testing a semiconductor die and are adapted to establish an electrical connection with the bond pads of the die. In a second embodiment, the contact pins are formed directly on the bond pads of a die and can be used for establishing a permanent or temporary electrical connection to the pads. The contact pins include a base portion attached to the die or interconnect, a compliant spring segment, and a contact ball at the tip. The contact pins are formed using a wire bonding process or a welding process in which a metal wire is simultaneously heated and shaped into a compliant structure as it is attached to the die or interconnect.
摘要:
A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used.
摘要:
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
摘要:
An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on ICs at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the ICs. The ID codes of the ICs are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the ICs is then accessed, and additional repair procedures the ICs may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
摘要:
Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.