公开(公告)号：US11362061B2

公开(公告)日：2022-06-14

申请号：US16906387

申请日：2020-06-19

申请人： IMEC vzw ,  Katholieke Universiteit Leuven

发明人： Lin Hou ,  Jaber Derakhshandeh ,  Eric Beyne ,  Ingrid De Wolf ,  Giovanni Capuz

IPC分类号： H01L23/00

摘要： A method is disclosed for electrically bonding a first semiconductor component to a second semiconductor component, both components including arrays of contact areas. In one aspect, prior to bonding, layers of an intermetallic compound are formed on the contact areas of the second component. The roughness of the intermetallic layers is such that the intermetallic layers include cavities suitable for insertion of a solder material in the cavities, under the application of a bonding pressure, when the solder is at a temperature below its melting temperature. The components are aligned and bonded, while the solder material is applied between the two. Bonding takes place at a temperature below the melting temperature of the solder. The bond can be established only by the insertion of the solder into the cavities of the intermetallic layers, and without the formation of a second intermetallic layer.

公开(公告)号：US09978710B2

公开(公告)日：2018-05-22

申请号：US15385653

申请日：2016-12-20

申请人： IMEC VZW ,  Katholieke Universiteit Leuven

发明人： Vikas Dubey ,  Eric Beyne ,  Jaber Derakhshandeh

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/81 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03424 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/0601 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13009 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13541 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16058 ,  H01L2224/16112 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/8114 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2924/01049 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01005 ,  H01L2924/206 ,  H01L2924/20106 ,  H01L2924/207

摘要： A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.

公开(公告)号：US20170194283A1

公开(公告)日：2017-07-06

申请号：US15385653

申请日：2016-12-20

申请人： IMEC VZW ,  Katholieke Universiteit Leuven

发明人： Vikas Dubey ,  Eric Beyne ,  Jaber Derakhshandeh

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498

CPC分类号： H01L24/81 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03424 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/0601 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13009 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13541 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16058 ,  H01L2224/16112 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/8114 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2924/01049 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01005 ,  H01L2924/206 ,  H01L2924/20106 ,  H01L2924/207

摘要： A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.

公开(公告)号：US10066303B2

公开(公告)日：2018-09-04

申请号：US14634535

申请日：2015-02-27

申请人： IMEC VZW ,  GLOBALFOUNDRIES INC.

发明人： Eric Beyne ,  Joeri De Vos ,  Jaber Derakhshandeh ,  Luke England ,  George Vakanas

IPC分类号： B32B15/00 ,  C23C30/00 ,  H01L23/00

摘要： The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.

公开(公告)号：US11810892B2

公开(公告)日：2023-11-07

申请号：US17102249

申请日：2020-11-23

申请人： IMEC vzw

发明人： Jaber Derakhshandeh ,  Eric Beyne ,  Gerald Peter Beyer

IPC分类号： H01L23/00 ,  B23K1/008 ,  H01L23/498 ,  B23K101/40

CPC分类号： H01L24/81 ,  B23K1/008 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/94 ,  H01L24/97 ,  B23K2101/40 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/06155 ,  H01L2224/1403 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/14177 ,  H01L2224/14515 ,  H01L2224/14517 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/1703 ,  H01L2224/17136 ,  H01L2224/17155 ,  H01L2224/17177 ,  H01L2224/17517 ,  H01L2224/8183 ,  H01L2224/8192 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81906 ,  H01L2224/81907

摘要： A method of bonding semiconductor components is described. In one aspect a first component, for example a semiconductor die, is bonded to a second component, for example a semiconductor wafer or another die, by direct metal-metal bonds between metal bumps on one component and corresponding bumps or contact pads on the other component. In addition, a number of solder bumps are provided on one of the components, and corresponding contact areas on the other component, and fast solidified solder connections are established between the solder bumps and the corresponding contact areas, without realizing the metal-metal bonds. The latter metal-metal bonds are established in a heating step performed after the soldering step. This enables a fast bonding process applied to multiple dies bonded on different areas of the wafer and/or stacked one on top of the other, followed by a single heating step for realizing metal-metal bonds between the respective dies and the wafer or between multiple stacked dies. The method allows to improve the throughput of the bonding process, as the heating step takes place only once for a plurality of dies and/or wafers.

公开(公告)号：US20210159207A1

公开(公告)日：2021-05-27

申请号：US17102249

申请日：2020-11-23

申请人： IMEC vzw

发明人： Jaber Derakhshandeh ,  Eric Beyne ,  Gerald Peter Beyer

IPC分类号： H01L23/00 ,  B23K1/008

摘要： A method of bonding semiconductor components is described. In one aspect a first component, for example a semiconductor die, is bonded to a second component, for example a semiconductor wafer or another die, by direct metal-metal bonds between metal bumps on one component and corresponding bumps or contact pads on the other component. In addition, a number of solder bumps are provided on one of the components, and corresponding contact areas on the other component, and fast solidified solder connections are established between the solder bumps and the corresponding contact areas, without realizing the metal-metal bonds. The latter metal-metal bonds are established in a heating step performed after the soldering step. This enables a fast bonding process applied to multiple dies bonded on different areas of the wafer and/or stacked one on top of the other, followed by a single heating step for realizing metal-metal bonds between the respective dies and the wafer or between multiple stacked dies. The method allows to improve the throughput of the bonding process, as the heating step takes place only once for a plurality of dies and/or wafers.

公开(公告)号：US20240297136A1

公开(公告)日：2024-09-05

申请号：US18591705

申请日：2024-02-29

申请人： IMEC VZW

发明人： Jaber Derakhshandeh ,  Vadiraj Manjunath Ananthapadmanabha Rao ,  Danny Wan ,  Eric Beyne ,  Kristiaan De Greve ,  Anton Potocnik

IPC分类号： H01L23/00 ,  H10N60/01 ,  H10N60/81

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H10N60/0912 ,  H10N60/815 ,  H01L2224/0401 ,  H01L2224/11009 ,  H01L2224/11462 ,  H01L2224/13109

摘要： Superconducting solder bumps are produced on a qubit substrate by electrodeposition. The substrate comprises qubit areas, and superconducting contact pads connected to the qubit areas. First a protection layer is formed on the substrate, and patterned so as to cover at least the qubit areas. Then one or more thin layers are deposited conformally on the patterned protection layer, the thin layers comprising at least a non-superconducting layer suitable for acting as a seed layer for the electrodeposition of the solder bumps. The seed layer is removed locally in areas which lie within the surface area of respective contact pads. This is done by producing and patterning a mask layer, so that openings are formed therein, and by removing the seed layer from the bottom of the openings. The solder bumps are formed by electrodeposition of the solder material on the bottom of the openings. After the formation of the solder bumps, the seed layer and the protection layer are removed.

公开(公告)号：US20240203965A1

公开(公告)日：2024-06-20

申请号：US18538422

申请日：2023-12-13

申请人： IMEC VZW

发明人： Jaber Derakhshandeh ,  Eric Beyne

IPC分类号： H01L25/16 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/162 ,  H01L21/7684 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/80895 ,  H01L2224/80896

摘要： A method for bonding and interconnecting micro-electronic components is provided. In one aspect, two substrates are bonded to form a 3D assembly of micro-electronic components. Both substrates include first cavities open to the respective bonding surfaces, and at least one substrate includes a second cavity that is larger than the first cavities in terms of its in-plane dimensions, and possibly also in terms of its depth. An electrically conductive layer is produced on each substrate. The layer is patterned in the second cavity, and a micro-electronic device is fabricated in the second cavity. The bonding surfaces are planarized, removing the conformal layer from the bonding surfaces, and the substrates are bonded to form the assembly, where the first cavities of both substrates are brought into mutual contact to form an electrical connection. Device in the large cavities may be contacted through TSV connections or back end of line interconnect levels.

公开(公告)号：US20230200263A1

公开(公告)日：2023-06-22

申请号：US18060389

申请日：2022-11-30

申请人： IMEC VZW

发明人： Jaber Derakhshandeh ,  Iuliana Radu ,  Eric Beyne ,  Bogdan Govoreanu

IPC分类号： H10N69/00 ,  H01L23/00 ,  H01L23/538

CPC分类号： H10N69/00 ,  H01L24/13 ,  H01L24/16 ,  H01L24/05 ,  H01L24/08 ,  H01L23/5384 ,  H01L24/14 ,  H01L24/06 ,  H01L2224/13109 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/05609 ,  H01L2224/08225 ,  H01L2224/0557 ,  H01L2224/06181

摘要： The present disclosure relates to a quantum bit (qubit) chip. The qubit chip includes two or more qubit wafers arranged along a common axis and one or more spacer elements. The spacer elements and the qubit wafers are alternately arranged on the common axis. The qubit chip further includes a conductive arrangement configured to electrically connect the two or more qubit wafers, where the conductive arrangement includes at least one superconducting via per each qubit wafer of the two or more qubit wafers and each spacer element of the one or more spacer elements, the at least one superconducting via passing through the qubit wafer or spacer element.

公开(公告)号：US20150247244A1

公开(公告)日：2015-09-03

申请号：US14634535

申请日：2015-02-27

申请人： IMEC VZW ,  GLOBALFOUNDRIES INC.

发明人： Eric Beyne ,  Joeri De Vos ,  Jaber Derakhshandeh ,  Luke England ,  George Vakanas

IPC分类号： C23C30/00

CPC分类号： C23C30/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/031 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05147 ,  H01L2224/05149 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/0518 ,  H01L2224/05563 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/13101 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13144 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48655 ,  H01L2224/48657 ,  H01L2224/48755 ,  H01L2224/48757 ,  H01L2224/48855 ,  H01L2224/48857 ,  H01L2224/81203 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85355 ,  H01L2224/85375 ,  H01L2224/85455 ,  H01L2224/85457 ,  Y10T428/12826 ,  Y10T428/12861 ,  Y10T428/12882 ,  Y10T428/1291 ,  Y10T428/12931 ,  Y10T428/12944 ,  Y10T428/24917 ,  H01L2924/01005 ,  H01L2924/00014 ,  H01L2924/014

摘要： The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.

摘要翻译： 本发明涉及一种具有至少一个主表面的基底，该至少一个主表面包括由覆盖层覆盖的至少一个非贵金属粘结着陆垫，从而将非贵金属粘合着陆垫与环境隔离。 该覆盖层包括合金，该合金为NiB或CoB，并且含有10％至5​​0％范围内的硼的原子浓度百分比。